mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
Add a bunch of patterns for F64 FP ops, add some more integer ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
237733e933
commit
67ab118a6d
@ -240,8 +240,9 @@ class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, OL, asmstr>;
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class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
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: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
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let Pattern = pt;
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}
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class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
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@ -290,9 +291,10 @@ class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, OL, asmstr> {
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}
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class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
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: XForm_base_r3xo<opcode, xo, OL, asmstr> {
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let A = 0;
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let Pattern = pt;
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}
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class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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@ -463,13 +465,16 @@ class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
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}
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// 1.7.12 A-Form
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class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
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class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
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list<dag> pattern>
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: I<opcode, OL, asmstr> {
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bits<5> FRT;
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bits<5> FRA;
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bits<5> FRC;
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bits<5> FRB;
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let Pattern = pattern;
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bit RC = 0; // set by isDOT
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let Inst{6-10} = FRT;
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@ -480,13 +485,13 @@ class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
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let Inst{31} = RC;
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}
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class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
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: AForm_1<opcode, xo, OL, asmstr> {
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class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
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: AForm_1<opcode, xo, OL, asmstr, pat> {
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let FRC = 0;
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}
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class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
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: AForm_1<opcode, xo, OL, asmstr> {
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class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
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: AForm_1<opcode, xo, OL, asmstr, pat> {
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let FRB = 0;
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}
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@ -76,6 +76,9 @@ def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
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SDTCisSameAs<0, 1>, SDTCisInt<0>
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]>;
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def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
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SDTCisSameAs<0, 1>, SDTCisFP<0>
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]>;
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def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
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SDTCisVTSmallerThanOp<2, 1>
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@ -117,6 +120,9 @@ def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
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def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
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def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
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def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
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def and : SDNode<"ISD::AND" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp,
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@ -128,6 +134,9 @@ def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
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def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
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def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
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def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
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def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
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def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
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def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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@ -533,19 +542,19 @@ def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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[]>, isPPC64;
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB",
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[]>;
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[(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
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def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB",
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[]>, isPPC64;
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def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srw $rA, $rS, $rB",
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[]>;
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[(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
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def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB",
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[]>, isPPC64;
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def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sraw $rA, $rS, $rB",
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[]>;
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[(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
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let isStore = 1 in {
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stbx $rS, $rA, $rB">;
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@ -561,7 +570,8 @@ def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB">, isPPC64;
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}
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def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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"srawi $rA, $rS, $SH">;
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"srawi $rA, $rS, $SH",
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[(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
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def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
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"cntlzw $rA, $rS",
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[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
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@ -597,25 +607,35 @@ def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfdx $dst, $base, $index">;
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}
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def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
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"fcfid $frD, $frB">, isPPC64;
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"fcfid $frD, $frB",
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[]>, isPPC64;
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def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
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"fctidz $frD, $frB">, isPPC64;
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"fctidz $frD, $frB",
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[]>, isPPC64;
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def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
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"fctiwz $frD, $frB">;
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"fctiwz $frD, $frB",
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[]>;
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def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
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"fabs $frD, $frB">;
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"fabs $frD, $frB",
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[(set FPRC:$frD, (fabs FPRC:$frB))]>;
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def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
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"fmr $frD, $frB">;
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"fmr $frD, $frB",
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[]>; // (set FPRC:$frD, FPRC:$frB)
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def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
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"fnabs $frD, $frB">;
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"fnabs $frD, $frB",
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[(set FPRC:$frD, (fneg (fabs FPRC:$frB)))]>;
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def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
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"fneg $frD, $frB">;
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"fneg $frD, $frB",
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[(set FPRC:$frD, (fneg FPRC:$frB))]>;
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def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
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"frsp $frD, $frB">;
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"frsp $frD, $frB",
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[]>;
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def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
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"fsqrt $frD, $frB">;
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"fsqrt $frD, $frB",
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[(set FPRC:$frD, (fsqrt FPRC:$frB))]>;
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def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
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"fsqrts $frD, $frB">;
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"fsqrts $frD, $frB",
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[]>;
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let isStore = 1 in {
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def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
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@ -711,55 +731,76 @@ def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
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//
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def FMADD : AForm_1<63, 29,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fmadd $FRT, $FRA, $FRC, $FRB">;
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"fmadd $FRT, $FRA, $FRC, $FRB",
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[(set FPRC:$FRT, (fadd (fmul FPRC:$FRA, FPRC:$FRC),
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FPRC:$FRB))]>;
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def FMADDS : AForm_1<59, 29,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fmadds $FRT, $FRA, $FRC, $FRB">;
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"fmadds $FRT, $FRA, $FRC, $FRB",
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[]>;
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def FMSUB : AForm_1<63, 28,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fmsub $FRT, $FRA, $FRC, $FRB">;
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"fmsub $FRT, $FRA, $FRC, $FRB",
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[(set FPRC:$FRT, (fsub (fmul FPRC:$FRA, FPRC:$FRC),
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FPRC:$FRB))]>;
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def FMSUBS : AForm_1<59, 28,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fmsubs $FRT, $FRA, $FRC, $FRB">;
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"fmsubs $FRT, $FRA, $FRC, $FRB",
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[]>;
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def FNMADD : AForm_1<63, 31,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fnmadd $FRT, $FRA, $FRC, $FRB">;
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"fnmadd $FRT, $FRA, $FRC, $FRB",
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[(set FPRC:$FRT, (fneg (fadd (fmul FPRC:$FRA, FPRC:$FRC),
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FPRC:$FRB)))]>;
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def FNMADDS : AForm_1<59, 31,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fnmadds $FRT, $FRA, $FRC, $FRB">;
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"fnmadds $FRT, $FRA, $FRC, $FRB",
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[]>;
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def FNMSUB : AForm_1<63, 30,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fnmsub $FRT, $FRA, $FRC, $FRB">;
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"fnmsub $FRT, $FRA, $FRC, $FRB",
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[(set FPRC:$FRT, (fneg (fsub (fmul FPRC:$FRA, FPRC:$FRC),
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FPRC:$FRB)))]>;
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def FNMSUBS : AForm_1<59, 30,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fnmsubs $FRT, $FRA, $FRC, $FRB">;
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"fnmsubs $FRT, $FRA, $FRC, $FRB",
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[]>;
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def FSEL : AForm_1<63, 23,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
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"fsel $FRT, $FRA, $FRC, $FRB">;
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"fsel $FRT, $FRA, $FRC, $FRB",
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[]>;
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def FADD : AForm_2<63, 21,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fadd $FRT, $FRA, $FRB">;
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"fadd $FRT, $FRA, $FRB",
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[(set FPRC:$FRT, (fadd FPRC:$FRA, FPRC:$FRB))]>;
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def FADDS : AForm_2<59, 21,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fadds $FRT, $FRA, $FRB">;
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"fadds $FRT, $FRA, $FRB",
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[]>;
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def FDIV : AForm_2<63, 18,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fdiv $FRT, $FRA, $FRB">;
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"fdiv $FRT, $FRA, $FRB",
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[(set FPRC:$FRT, (fdiv FPRC:$FRA, FPRC:$FRB))]>;
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def FDIVS : AForm_2<59, 18,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fdivs $FRT, $FRA, $FRB">;
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"fdivs $FRT, $FRA, $FRB",
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[]>;
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def FMUL : AForm_3<63, 25,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fmul $FRT, $FRA, $FRB">;
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"fmul $FRT, $FRA, $FRB",
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[(set FPRC:$FRT, (fmul FPRC:$FRA, FPRC:$FRB))]>;
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def FMULS : AForm_3<59, 25,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fmuls $FRT, $FRA, $FRB">;
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"fmuls $FRT, $FRA, $FRB",
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[]>;
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def FSUB : AForm_2<63, 20,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fsub $FRT, $FRA, $FRB">;
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"fsub $FRT, $FRA, $FRB",
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[(set FPRC:$FRT, (fsub FPRC:$FRA, FPRC:$FRB))]>;
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def FSUBS : AForm_2<59, 20,
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(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
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"fsubs $FRT, $FRA, $FRB">;
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"fsubs $FRT, $FRA, $FRB",
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[]>;
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// M-Form instructions. rotate and mask instructions.
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//
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