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https://github.com/c64scene-ar/llvm-6502.git
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[ARM] - Fix lowering of shufflevectors in AArch32
Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Luke Cheeseman
parent
ca2a3eb2e7
commit
67b17f9ff8
@ -5043,18 +5043,50 @@ static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
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return VT == MVT::v8i8 && M.size() == 8;
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}
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// Checks whether the shuffle mask represents a vector transpose (VTRN) by
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// checking that pairs of elements in the shuffle mask represent the same index
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// in each vector, incrementing the expected index by 2 at each step.
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// e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
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// v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
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// v2={e,f,g,h}
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// WhichResult gives the offset for each element in the mask based on which
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// of the two results it belongs to.
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//
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// The transpose can be represented either as:
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// result1 = shufflevector v1, v2, result1_shuffle_mask
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// result2 = shufflevector v1, v2, result2_shuffle_mask
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// where v1/v2 and the shuffle masks have the same number of elements
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// (here WhichResult (see below) indicates which result is being checked)
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//
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// or as:
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// results = shufflevector v1, v2, shuffle_mask
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// where both results are returned in one vector and the shuffle mask has twice
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// as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
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// want to check the low half and high half of the shuffle mask as if it were
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// the other case
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static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
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unsigned EltSz = VT.getVectorElementType().getSizeInBits();
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if (EltSz == 64)
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
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return false;
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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// If the mask is twice as long as the result then we need to check the upper
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// and lower parts of the mask
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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for (unsigned j = 0; j < NumElts; j += 2) {
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if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
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(M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
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return false;
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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return true;
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}
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@ -5067,28 +5099,52 @@ static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
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return false;
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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for (unsigned j = 0; j < NumElts; j += 2) {
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if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
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(M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
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return false;
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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return true;
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}
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// Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
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// that the mask elements are either all even and in steps of size 2 or all odd
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// and in steps of size 2.
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// e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
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// v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
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// v2={e,f,g,h}
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// Requires similar checks to that of isVTRNMask with
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// respect the how results are returned.
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static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
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unsigned EltSz = VT.getVectorElementType().getSizeInBits();
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if (EltSz == 64)
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i != NumElts; ++i) {
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if (M[i] < 0) continue; // ignore UNDEF indices
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if ((unsigned) M[i] != 2 * i + WhichResult)
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return false;
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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for (unsigned j = 0; j < NumElts; ++j) {
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if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
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return false;
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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// VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && EltSz == 32)
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return false;
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@ -5104,18 +5160,27 @@ static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
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if (EltSz == 64)
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return false;
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unsigned Half = VT.getVectorNumElements() / 2;
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned j = 0; j != 2; ++j) {
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unsigned Idx = WhichResult;
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for (unsigned i = 0; i != Half; ++i) {
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int MIdx = M[i + j * Half];
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if (MIdx >= 0 && (unsigned) MIdx != Idx)
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return false;
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Idx += 2;
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unsigned NumElts = VT.getVectorNumElements();
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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unsigned Half = NumElts / 2;
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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for (unsigned j = 0; j < NumElts; j += Half) {
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unsigned Idx = WhichResult;
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for (unsigned k = 0; k < Half; ++k) {
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int MIdx = M[i + j + k];
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if (MIdx >= 0 && (unsigned) MIdx != Idx)
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return false;
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Idx += 2;
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}
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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// VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && EltSz == 32)
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return false;
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@ -5123,21 +5188,37 @@ static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
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return true;
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}
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// Checks whether the shuffle mask represents a vector zip (VZIP) by checking
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// that pairs of elements of the shufflemask represent the same index in each
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// vector incrementing sequentially through the vectors.
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// e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
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// v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
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// v2={e,f,g,h}
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// Requires similar checks to that of isVTRNMask with respect the how results
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// are returned.
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static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
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unsigned EltSz = VT.getVectorElementType().getSizeInBits();
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if (EltSz == 64)
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned i = 0; i != NumElts; i += 2) {
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if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
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return false;
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Idx += 1;
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned j = 0; j < NumElts; j += 2) {
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if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
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(M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
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return false;
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Idx += 1;
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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// VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && EltSz == 32)
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return false;
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@ -5154,15 +5235,23 @@ static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned i = 0; i != NumElts; i += 2) {
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if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
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return false;
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Idx += 1;
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if (M.size() != NumElts && M.size() != NumElts*2)
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return false;
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for (unsigned i = 0; i < M.size(); i += NumElts) {
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WhichResult = M[i] == 0 ? 0 : 1;
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned j = 0; j < NumElts; j += 2) {
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if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
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(M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
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return false;
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Idx += 1;
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}
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}
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if (M.size() == NumElts*2)
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WhichResult = 0;
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// VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
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if (VT.is64BitVector() && EltSz == 32)
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return false;
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@ -196,3 +196,35 @@ define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>
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store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
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ret void
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}
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define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_reverse_and_extract
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; CHECK-NOT: vtrn
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; CHECK: vrev
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0>
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ret <4 x i32> %0
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}
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define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_dup_and_extract
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; CHECK-NOT: vtrn
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; CHECK: vdup
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x i32> %0
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}
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define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: test_zip_and_extract
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; CHECK: vzip
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; CHECK: vext
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1>
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ret <4 x i32> %0
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}
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@ -325,3 +325,13 @@ define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
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ret <16 x i16> %tmp3
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}
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define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
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entry:
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; CHECK-LABEL: vtrn_lower_shufflemask_undef
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; CHECK: vtrn
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7>
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ret <8 x i16> %0
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}
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@ -264,3 +264,24 @@ define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
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ret <16 x i16> %tmp3
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}
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define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
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entry:
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; CHECK-LABEL: vuzp_lower_shufflemask_undef
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; CHECK: vuzp
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>
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ret <8 x i16> %0
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}
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define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) {
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entry:
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; CHECK-LABEL: vuzp_lower_shufflemask_zeroed
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; CHECK-NOT: vtrn
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; CHECK: vuzp
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3>
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ret <4 x i32> %0
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}
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@ -264,3 +264,34 @@ define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
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ret <32 x i8> %tmp3
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}
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define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_undef
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; CHECK: vzip
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
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ret <8 x i16> %0
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}
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define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_zeroed
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; CHECK-NOT: vtrn
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; CHECK: vzip
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
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ret <4 x i32> %0
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}
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define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) {
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_vuzp
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; CHECK-NOT: vuzp
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; CHECK: vzip
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 0>
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ret <4 x i32> %0
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}
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