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- MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode.
- Remove the ugly TargetInstrDescriptors hack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32032 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -299,7 +299,7 @@ public:
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/// MachineInstr - Representation of each machine instruction.
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/// MachineInstr - Representation of each machine instruction.
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///
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///
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class MachineInstr {
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class MachineInstr {
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short Opcode; // the opcode
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const TargetInstrDescriptor *TID; // Instruction descriptor.
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unsigned short NumImplicitOps; // Number of implicit operands (which
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unsigned short NumImplicitOps; // Number of implicit operands (which
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// are determined at construction time).
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// are determined at construction time).
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@ -319,7 +319,7 @@ class MachineInstr {
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public:
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public:
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// opcode 0 and no operands.
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/// TID NULL and no operands.
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MachineInstr();
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MachineInstr();
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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@ -337,10 +337,14 @@ public:
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const MachineBasicBlock* getParent() const { return parent; }
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const MachineBasicBlock* getParent() const { return parent; }
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MachineBasicBlock* getParent() { return parent; }
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MachineBasicBlock* getParent() { return parent; }
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/// getInstrDescriptor - Returns the target instruction descriptor of this
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/// MachineInstr.
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const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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///
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const int getOpcode() const { return Opcode; }
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const int getOpcode() const;
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/// Access to explicit operands of the instruction.
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/// Access to explicit operands of the instruction.
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///
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///
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@ -500,9 +504,10 @@ public:
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// Accessors used to modify instructions in place.
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// Accessors used to modify instructions in place.
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//
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//
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
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/// the current instruction with a new one.
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///
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///
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void setOpcode(unsigned Op) { Opcode = Op; }
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void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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/// fewer operand than it started with.
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@ -525,7 +530,7 @@ private:
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/// addImplicitDefUseOperands - Add all implicit def and use operands to
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/// addImplicitDefUseOperands - Add all implicit def and use operands to
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/// this instruction.
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/// this instruction.
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void addImplicitDefUseOperands(const TargetInstrDescriptor &TID);
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void addImplicitDefUseOperands();
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};
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -21,28 +21,17 @@
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#include <iostream>
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#include <iostream>
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using namespace llvm;
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using namespace llvm;
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class TargetInstrInfo.
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//
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// FIXME: This should be a property of the target so that more than one target
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// at a time can be active...
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//
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namespace llvm {
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extern const TargetInstrDescriptor *TargetInstrDescriptors;
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}
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// opcode 0 and no operands.
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/// TID NULL and no operands.
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MachineInstr::MachineInstr()
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MachineInstr::MachineInstr()
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: Opcode(0), NumImplicitOps(0), parent(0) {
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: TID(0), NumImplicitOps(0), parent(0) {
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// Make sure that we get added to a machine basicblock
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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LeakDetector::addGarbageObject(this);
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}
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}
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void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
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void MachineInstr::addImplicitDefUseOperands() {
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if (TID.ImplicitDefs)
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs) {
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) {
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MachineOperand Op;
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = true;
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Op.IsDef = true;
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@ -53,8 +42,8 @@ void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
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Op.offset = 0;
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Op.offset = 0;
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Operands.push_back(Op);
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Operands.push_back(Op);
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}
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}
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if (TID.ImplicitUses)
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses) {
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) {
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MachineOperand Op;
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = false;
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Op.IsDef = false;
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@ -71,16 +60,16 @@ void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
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/// implicit operands. It reserves space for number of operands specified by
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDescriptor or the numOperands if it is not zero. (for
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/// TargetInstrDescriptor or the numOperands if it is not zero. (for
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/// instructions with variable number of operands).
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/// instructions with variable number of operands).
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MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
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MachineInstr::MachineInstr(const TargetInstrDescriptor &tid)
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: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
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: TID(&tid), NumImplicitOps(0), parent(0) {
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if (TID.ImplicitDefs)
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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NumImplicitOps++;
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if (TID.ImplicitUses)
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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NumImplicitOps++;
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID.numOperands);
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Operands.reserve(NumImplicitOps + TID->numOperands);
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addImplicitDefUseOperands(TID);
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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LeakDetector::addGarbageObject(this);
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}
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}
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@ -89,17 +78,17 @@ MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
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/// MachineInstr is created and added to the end of the specified basic block.
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB,
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MachineInstr::MachineInstr(MachineBasicBlock *MBB,
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const TargetInstrDescriptor &TID)
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const TargetInstrDescriptor &tid)
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: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
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: TID(&tid), NumImplicitOps(0), parent(0) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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if (TID.ImplicitDefs)
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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NumImplicitOps++;
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if (TID.ImplicitUses)
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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NumImplicitOps++;
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID.numOperands);
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Operands.reserve(NumImplicitOps + TID->numOperands);
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addImplicitDefUseOperands(TID);
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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LeakDetector::addGarbageObject(this);
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MBB->push_back(this); // Add instruction to end of basic block!
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MBB->push_back(this); // Add instruction to end of basic block!
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@ -108,7 +97,7 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB,
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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///
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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Opcode = MI.getOpcode();
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TID = MI.getInstrDescriptor();
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NumImplicitOps = MI.NumImplicitOps;
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NumImplicitOps = MI.NumImplicitOps;
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Operands.reserve(MI.getNumOperands());
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Operands.reserve(MI.getNumOperands());
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@ -127,6 +116,12 @@ MachineInstr::~MachineInstr() {
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LeakDetector::removeGarbageObject(this);
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LeakDetector::removeGarbageObject(this);
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}
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}
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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const int MachineInstr::getOpcode() const {
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return TID->Opcode;
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}
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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/// block, and returns it, but does not delete it.
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MachineInstr *MachineInstr::removeFromParent() {
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MachineInstr *MachineInstr::removeFromParent() {
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@ -139,8 +134,8 @@ MachineInstr *MachineInstr::removeFromParent() {
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/// OperandComplete - Return true if it's illegal to add a new operand
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/// OperandComplete - Return true if it's illegal to add a new operand
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///
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///
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bool MachineInstr::OperandsComplete() const {
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bool MachineInstr::OperandsComplete() const {
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unsigned short NumOperands = TargetInstrDescriptors[Opcode].numOperands;
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unsigned short NumOperands = TID->numOperands;
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if ((TargetInstrDescriptors[Opcode].Flags & M_VARIABLE_OPS) == 0 &&
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if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
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getNumOperands()-NumImplicitOps >= NumOperands)
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getNumOperands()-NumImplicitOps >= NumOperands)
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return true; // Broken: we have all the operands of this instruction!
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return true; // Broken: we have all the operands of this instruction!
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return false;
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return false;
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@ -241,10 +236,8 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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++StartOp; // Don't print this operand again!
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++StartOp; // Don't print this operand again!
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}
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}
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// Must check if Target machine is not null because machine BB could not
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if (TID)
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// be attached to a Machine function yet
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OS << TID->Name;
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if (TM)
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OS << TM->getInstrInfo()->getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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const MachineOperand& mop = getOperand(i);
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@ -294,7 +287,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
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// Otherwise, print it out in the "raw" format without symbolic register names
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// Otherwise, print it out in the "raw" format without symbolic register names
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// and such.
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// and such.
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os << TargetInstrDescriptors[MI.getOpcode()].Name;
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os << MI.getInstrDescriptor()->Name;
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for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
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for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
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os << "\t" << MI.getOperand(i);
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os << "\t" << MI.getOperand(i);
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