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Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196858 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
2013-12-10 01:13:59 +00:00
parent d5cf7abce6
commit 6806e11612
2 changed files with 28 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -9859,7 +9859,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
if (N->getNumOperands() == 2 &&
N->getOperand(1)->getOpcode() == ISD::UNDEF) {
SDValue In = N->getOperand(0);
assert(In->getValueType(0).isVector() && "Must concat vectors");
assert(In.getValueType().isVector() && "Must concat vectors");
// Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
if (In->getOpcode() == ISD::BITCAST &&