mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-25 13:24:46 +00:00
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -1160,7 +1160,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
|
||||
abort();
|
||||
case 1:
|
||||
return SDOperand(); // ret void is legal
|
||||
case 2: {
|
||||
case 3: {
|
||||
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
|
||||
unsigned ArgReg;
|
||||
if (MVT::isVector(ArgVT))
|
||||
@@ -1180,8 +1180,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
|
||||
DAG.getMachineFunction().addLiveOut(ArgReg);
|
||||
break;
|
||||
}
|
||||
case 3:
|
||||
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
|
||||
case 5:
|
||||
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
|
||||
SDOperand());
|
||||
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
|
||||
// If we haven't noted the R3+R4 are live out, do so now.
|
||||
|
Reference in New Issue
Block a user