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https://github.com/c64scene-ar/llvm-6502.git
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support for larger calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19932 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
bbec41dbac
commit
684f229895
@ -27,6 +27,7 @@
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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@ -138,34 +139,42 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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SDOperand newroot, argt;
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++count;
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assert(count <= 6 && "More than 6 args not supported");
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switch (getValueType(I->getType())) {
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default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
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case MVT::f64:
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case MVT::f32:
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count - 1]);
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argOpc.push_back(Alpha::CPYS);
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newroot = DAG.getCopyFromReg(argVreg[count-1], getValueType(I->getType()), DAG.getRoot());
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
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argPreg.push_back(args_int[count - 1]);
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argOpc.push_back(Alpha::BIS);
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argt = newroot = DAG.getCopyFromReg(argVreg[count-1], MVT::i64, DAG.getRoot());
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if (getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
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break;
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if (count < 6) {
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switch (getValueType(I->getType())) {
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default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
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case MVT::f64:
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case MVT::f32:
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count]);
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argOpc.push_back(Alpha::CPYS);
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newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
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argPreg.push_back(args_int[count]);
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argOpc.push_back(Alpha::BIS);
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argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
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if (getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
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break;
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}
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} else { //more args
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
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// Create the SelectionDAG nodes corresponding to a load from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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argt = newroot = DAG.getLoad(getValueType(I->getType()), DAG.getEntryNode(), FIN);
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}
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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++count;
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}
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BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
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@ -181,6 +190,9 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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int NumBytes = 0;
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if (Args.size() > 6)
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NumBytes = (Args.size() - 6) * 8;
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Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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@ -404,9 +416,9 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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//STL LDS
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//STQ LDT
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Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL;
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BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx);
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BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx);
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BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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//The easy way: doesn't work
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// //so these instructions are not supported on ev56
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@ -467,7 +479,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FrameIndex:
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1);
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BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1).addReg(Alpha::F31);
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return Result;
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case ISD::EXTLOAD:
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@ -576,32 +588,56 @@ unsigned ISel::SelectExpr(SDOperand N) {
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for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
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argvregs.push_back(SelectExpr(N.getOperand(i)));
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for(int i = 0, e = argvregs.size(); i < e; ++i)
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{
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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switch(N.getOperand(i+2).getValueType()) {
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default:
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Node->dump();
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N.getOperand(i).Val->dump();
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std::cerr << "Type for " << i << " is: " << N.getOperand(i+2).getValueType() << "\n";
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assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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case MVT::f32:
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case MVT::f64:
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BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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}
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}
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//in reg args
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for(int i = 0, e = std::min(6, (int)argvregs.size()); i < e; ++i)
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{
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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switch(N.getOperand(i+2).getValueType()) {
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default:
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Node->dump();
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N.getOperand(i).Val->dump();
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std::cerr << "Type for " << i << " is: " << N.getOperand(i+2).getValueType() << "\n";
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assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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case MVT::f32:
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case MVT::f64:
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BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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}
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}
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//in mem args
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for (int i = 6, e = argvregs.size(); i < e; ++i)
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{
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switch(N.getOperand(i+2).getValueType()) {
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default:
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Node->dump();
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N.getOperand(i).Val->dump();
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std::cerr << "Type for " << i << " is: " << N.getOperand(i+2).getValueType() << "\n";
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assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
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break;
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case MVT::f32:
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BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
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break;
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case MVT::f64:
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BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
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break;
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}
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}
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//build the right kind of call
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
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@ -49,7 +49,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, int FrameIdx) const {
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//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx);
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BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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// assert(0 && "TODO");
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}
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@ -59,7 +59,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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unsigned DestReg, int FrameIdx) const{
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//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
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BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx);
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BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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// assert(0 && "TODO");
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}
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@ -128,53 +128,35 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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void
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AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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assert(0 && "TODO");
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// unsigned i = 0;
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// MachineInstr &MI = *II;
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// MachineBasicBlock &MBB = *MI.getParent();
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// MachineFunction &MF = *MBB.getParent();
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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// while (!MI.getOperand(i).isFrameIndex()) {
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// ++i;
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// assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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// }
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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// int FrameIndex = MI.getOperand(i).getFrameIndex();
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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// MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// // Take into account whether it's an add or mem instruction
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// unsigned OffIdx = (i == 2) ? 1 : 2;
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// // Now add the frame object offset to the offset from r1.
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// int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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// MI.getOperand(OffIdx).getImmedValue();
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// // If we're not using a Frame Pointer that has been set to the value of the
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// // SP before having the stack size subtracted from it, then add the stack size
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// // to Offset to get the correct offset.
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// Offset += MF.getFrameInfo()->getStackSize();
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// Add the base register of R30 (SP) or R15 (FP).
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MI.SetMachineOperandReg(i + 1, hasFP(MF) ? Alpha::R15 : Alpha::R30);
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// if (Offset > 32767 || Offset < -32768) {
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// // Insert a set of r0 with the full offset value before the ld, st, or add
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// MachineBasicBlock *MBB = MI.getParent();
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// MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
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// MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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// .addImm(Offset));
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// // convert into indexed form of the instruction
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// // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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// unsigned NewOpcode =
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// const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
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// assert(NewOpcode && "No indexed form of load or store available!");
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// MI.setOpcode(NewOpcode);
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// MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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// MI.SetMachineOperandReg(2, PPC::R0);
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// } else {
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// MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
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// Offset);
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// }
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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if (Offset > 32767 || Offset < -32768) {
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std::cerr << "Offset needs to be " << Offset << "\n";
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assert(0 && "stack too big");
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} else {
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MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
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}
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}
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@ -191,6 +173,14 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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if (MFI->hasCalls()) {
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// We reserve argument space for call sites in the function immediately on
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// entry to the current function. This eliminates the need for add/sub
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// brackets around call sites.
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NumBytes += MFI->getMaxCallFrameSize();
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std::cerr << "Added " << MFI->getMaxCallFrameSize() << " to the stack due to calls\n";
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}
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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