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ARM getOperandLatency rewrite.
Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
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Andrew Trick
parent
f377071bf8
commit
68b16541cc
@ -2565,84 +2565,14 @@ static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
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return II;
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}
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int
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ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI,
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unsigned UseIdx) const {
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if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
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DefMI->isRegSequence() || DefMI->isImplicitDef()) {
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return 1;
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}
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// No operand latency. The caller may fall back to getInstrLatency.
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if (!ItinData || ItinData->isEmpty())
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return -1;
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const MCInstrDesc *DefMCID = &DefMI->getDesc();
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const MCInstrDesc *UseMCID = &UseMI->getDesc();
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const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
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unsigned Reg = DefMO.getReg();
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if (Reg == ARM::CPSR) {
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if (DefMI->getOpcode() == ARM::FMSTAT) {
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// fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
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return Subtarget.isCortexA9() ? 1 : 20;
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}
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// CPSR set and branch can be paired in the same cycle.
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if (UseMI->isBranch())
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return 0;
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// Otherwise it takes the instruction latency (generally one).
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unsigned Latency = getInstrLatency(ItinData, DefMI);
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// For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
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// its uses. Instructions which are otherwise scheduled between them may
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// incur a code size penalty (not able to use the CPSR setting 16-bit
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// instructions).
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if (Latency > 0 && Subtarget.isThumb2()) {
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const MachineFunction *MF = DefMI->getParent()->getParent();
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if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
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--Latency;
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}
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return Latency;
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}
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unsigned DefAlign = DefMI->hasOneMemOperand()
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? (*DefMI->memoperands_begin())->getAlignment() : 0;
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unsigned UseAlign = UseMI->hasOneMemOperand()
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? (*UseMI->memoperands_begin())->getAlignment() : 0;
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unsigned DefAdj = 0;
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if (DefMI->isBundle()) {
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DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
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if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
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DefMI->isRegSequence() || DefMI->isImplicitDef())
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return 1;
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DefMCID = &DefMI->getDesc();
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}
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unsigned UseAdj = 0;
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if (UseMI->isBundle()) {
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unsigned NewUseIdx;
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const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
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Reg, NewUseIdx, UseAdj);
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if (NewUseMI) {
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UseMI = NewUseMI;
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UseIdx = NewUseIdx;
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UseMCID = &UseMI->getDesc();
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}
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}
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int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
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*UseMCID, UseIdx, UseAlign);
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int Adj = DefAdj + UseAdj;
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if (Adj) {
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Latency -= (int)(DefAdj + UseAdj);
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if (Latency < 1)
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return 1;
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}
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if (Latency > 1 &&
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(Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
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/// Return the number of cycles to add to (or subtract from) the static
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/// itinerary based on the def opcode and alignment. The caller will ensure that
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/// adjusted latency is at least one cycle.
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static int adjustDefLatency(const ARMSubtarget &Subtarget,
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const MachineInstr *DefMI,
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const MCInstrDesc *DefMCID, unsigned DefAlign) {
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int Adjust = 0;
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if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) {
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// FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
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// variants are one cycle cheaper.
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switch (DefMCID->getOpcode()) {
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@ -2653,7 +2583,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
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if (ShImm == 0 ||
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(ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
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--Latency;
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--Adjust;
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break;
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}
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case ARM::t2LDRs:
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@ -2663,13 +2593,13 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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// Thumb2 mode: lsl only.
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unsigned ShAmt = DefMI->getOperand(3).getImm();
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if (ShAmt == 0 || ShAmt == 2)
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--Latency;
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--Adjust;
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break;
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}
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}
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}
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if (DefAlign < 8 && Subtarget.isCortexA9())
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if (DefAlign < 8 && Subtarget.isCortexA9()) {
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switch (DefMCID->getOpcode()) {
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default: break;
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case ARM::VLD1q8:
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@ -2778,10 +2708,97 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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case ARM::VLD4LNq32_UPD:
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// If the address is not 64-bit aligned, the latencies of these
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// instructions increases by one.
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++Latency;
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++Adjust;
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break;
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}
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}
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return Adjust;
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}
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int
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ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI,
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unsigned UseIdx) const {
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// No operand latency. The caller may fall back to getInstrLatency.
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if (!ItinData || ItinData->isEmpty())
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return -1;
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const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
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unsigned Reg = DefMO.getReg();
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const MCInstrDesc *DefMCID = &DefMI->getDesc();
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const MCInstrDesc *UseMCID = &UseMI->getDesc();
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unsigned DefAdj = 0;
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if (DefMI->isBundle()) {
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DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
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DefMCID = &DefMI->getDesc();
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}
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if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
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DefMI->isRegSequence() || DefMI->isImplicitDef()) {
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return 1;
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}
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unsigned UseAdj = 0;
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if (UseMI->isBundle()) {
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unsigned NewUseIdx;
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const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
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Reg, NewUseIdx, UseAdj);
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if (NewUseMI) {
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UseMI = NewUseMI;
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UseIdx = NewUseIdx;
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UseMCID = &UseMI->getDesc();
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}
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}
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if (Reg == ARM::CPSR) {
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if (DefMI->getOpcode() == ARM::FMSTAT) {
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// fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
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return Subtarget.isCortexA9() ? 1 : 20;
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}
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// CPSR set and branch can be paired in the same cycle.
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if (UseMI->isBranch())
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return 0;
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// Otherwise it takes the instruction latency (generally one).
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unsigned Latency = getInstrLatency(ItinData, DefMI);
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// For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
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// its uses. Instructions which are otherwise scheduled between them may
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// incur a code size penalty (not able to use the CPSR setting 16-bit
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// instructions).
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if (Latency > 0 && Subtarget.isThumb2()) {
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const MachineFunction *MF = DefMI->getParent()->getParent();
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if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
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--Latency;
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}
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return Latency;
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}
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unsigned DefAlign = DefMI->hasOneMemOperand()
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? (*DefMI->memoperands_begin())->getAlignment() : 0;
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unsigned UseAlign = UseMI->hasOneMemOperand()
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? (*UseMI->memoperands_begin())->getAlignment() : 0;
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// Get the itinerary's latency if possible, and handle variable_ops.
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int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
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*UseMCID, UseIdx, UseAlign);
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// Unable to find operand latency. The caller may resort to getInstrLatency.
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if (Latency < 0)
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return Latency;
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// Adjust for IT block position.
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int Adj = DefAdj + UseAdj;
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// Adjust for dynamic def-side opcode variants not captured by the itinerary.
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Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
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if (Adj >= 0 || (int)Latency > -Adj) {
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return Latency + Adj;
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}
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// Return the itinerary latency, which may be zero but not less than zero.
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return Latency;
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}
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@ -2981,8 +2998,9 @@ ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
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return 1;
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// If the second MI is predicated, then there is an implicit use dependency.
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return getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
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DepMI->getNumOperands());
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int Latency = getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
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DepMI->getNumOperands());
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return (Latency <= 0) ? 1 : Latency;
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}
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unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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@ -3023,7 +3041,16 @@ unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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return getNumMicroOps(ItinData, MI);
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}
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// For the common case, fall back on the itinerary's latency.
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return ItinData->getStageLatency(Class);
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unsigned Latency = ItinData->getStageLatency(Class);
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// Adjust for dynamic def-side opcode variants not captured by the itinerary.
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unsigned DefAlign = MI->hasOneMemOperand()
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? (*MI->memoperands_begin())->getAlignment() : 0;
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int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
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if (Adj >= 0 || (int)Latency > -Adj) {
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return Latency + Adj;
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}
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return Latency;
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}
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int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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