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On some targets (e.g. X86), shift amounts are not the same as the value
being shifted. Don't assume they are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24598 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -73,6 +73,9 @@ def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
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]>;
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def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
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]>;
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def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
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]>;
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@ -172,9 +175,9 @@ def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
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def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
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def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
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def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
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def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
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def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
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def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
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def and : SDNode<"ISD::AND" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp,
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