6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-15 06:29:05 +00:00
Code Issues Projects Releases Wiki Activity

Just use a single isMoveInstr to catch all the cases.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-07-27 00:05:15 +00:00
parent d83360694a
commit 68e3c6ae49
3 changed files with 12 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@@ -490,16 +490,21 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const { unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers. SrcSubIdx = DstSubIdx = 0; // No sub-registers.
unsigned oc = MI.getOpcode(); switch (MI.getOpcode()) {
if (oc == ARM::FCPYS || case ARM::FCPYS:
oc == ARM::FCPYD || case ARM::FCPYD:
oc == ARM::VMOVD || case ARM::VMOVD:
oc == ARM::VMOVQ) { case ARM::VMOVQ: {
SrcReg = MI.getOperand(1).getReg(); SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg(); DstReg = MI.getOperand(0).getReg();
return true; return true;
} }
else if (oc == getOpcode(ARMII::MOVr)) { case ARM::MOVr:
case ARM::tMOVr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVtgpr2gpr:
case ARM::tMOVgpr2gpr:
case ARM::t2MOVr: {
assert(MI.getDesc().getNumOperands() >= 2 && assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isReg() && MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() && MI.getOperand(1).isReg() &&
@@ -508,6 +513,7 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
DstReg = MI.getOperand(0).getReg(); DstReg = MI.getOperand(0).getReg();
return true; return true;
} }
}
return false; return false;
} }

23
lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@@ -71,29 +71,6 @@ Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
return false; return false;
} }
bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
unsigned oc = MI.getOpcode();
switch (oc) {
default:
return false;
case ARM::tMOVr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVtgpr2gpr:
case ARM::tMOVgpr2gpr:
assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
"Invalid Thumb MOV instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
}
unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const { int &FrameIndex) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {

3
lib/Target/ARM/Thumb1InstrInfo.h
View File

@@ -50,9 +50,6 @@ public:
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const; const std::vector<CalleeSavedInfo> &CSI) const;
bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI, unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,