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Add new function MachineInstrInfo::CreateZeroExtensionInstructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3582 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2002-09-05 18:36:41 +00:00
parent f36f06bb60
commit 68f716190b
2 changed files with 36 additions and 4 deletions
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20
include/llvm/Target/MachineInstrInfo.h
View File

@ -299,15 +299,31 @@ public:
// Create instruction sequence to produce a sign-extended register value // Create instruction sequence to produce a sign-extended register value
// from an arbitrary sized value (sized in bits, not bytes). // from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff. // Any stack space required is allocated via mcff.
// //
virtual void CreateSignExtensionInstructions(const TargetMachine& target, virtual void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F, Function* F,
Value* unsignedSrcVal, Value* srcVal,
unsigned int srcSizeInBits, unsigned int srcSizeInBits,
Value* dest, Value* dest,
std::vector<MachineInstr*>& mvec, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)const=0; MachineCodeForInstruction& mcfi) const=0;
// Create instruction sequence to produce a zero-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const=0;
}; };
#endif #endif

20
include/llvm/Target/TargetInstrInfo.h
View File

@ -299,15 +299,31 @@ public:
// Create instruction sequence to produce a sign-extended register value // Create instruction sequence to produce a sign-extended register value
// from an arbitrary sized value (sized in bits, not bytes). // from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff. // Any stack space required is allocated via mcff.
// //
virtual void CreateSignExtensionInstructions(const TargetMachine& target, virtual void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F, Function* F,
Value* unsignedSrcVal, Value* srcVal,
unsigned int srcSizeInBits, unsigned int srcSizeInBits,
Value* dest, Value* dest,
std::vector<MachineInstr*>& mvec, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)const=0; MachineCodeForInstruction& mcfi) const=0;
// Create instruction sequence to produce a zero-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const=0;
}; };
#endif #endif