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Fix more code to work properly with vector operands. Based on
a patch my Micah Villmow for PR6465. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97692 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1758,7 +1758,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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EVT VT = N1.getValueType();
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unsigned BitWidth = VT.getSizeInBits();
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unsigned BitWidth = VT.getScalarType().getSizeInBits();
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// fold vector ops
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if (VT.isVector()) {
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@ -1872,9 +1872,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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EVT MemVT = LN0->getMemoryVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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unsigned BitWidth = N1.getValueSizeInBits();
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unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
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if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
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BitWidth - MemVT.getSizeInBits())) &&
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BitWidth - MemVT.getScalarType().getSizeInBits())) &&
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((!LegalOperations && !LN0->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
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@ -1895,9 +1895,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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EVT MemVT = LN0->getMemoryVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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unsigned BitWidth = N1.getValueSizeInBits();
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unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
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if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
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BitWidth - MemVT.getSizeInBits())) &&
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BitWidth - MemVT.getScalarType().getSizeInBits())) &&
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((!LegalOperations && !LN0->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
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