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[AVX512] Add codegen test for the masking variant of valign

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The AddedComplexity is needed just like in avx512_perm_3src.  There may be a
bug in the complexity computation...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-08-07 23:18:18 +00:00
parent 43f6ce9289
commit 690499ed49
2 changed files with 12 additions and 2 deletions
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5
lib/Target/X86/X86InstrAVX512.td
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@ -8,8 +8,9 @@ multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
"$dst, "#IntelSrcAsm#"}",
[(set RC:$dst, RHS)]>;
let Constraints = "$src0 = $dst" in
def NAME#k: AVX512<O, F, Outs,
// Prefer over VMOV*rrk Pat<>
let Constraints = "$src0 = $dst", AddedComplexity = 20 in
def NAME#k: AVX512<O, F, Outs,
!con((ins RC:$src0, KRC:$mask), Ins),
OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
"$dst {${mask}}, "#IntelSrcAsm#"}",

9
test/CodeGen/X86/avx512-shuffle.ll
View File

@ -207,6 +207,15 @@ define <8 x double> @test16(<8 x double> %a, <8 x double> %b) nounwind {
ret <8 x double> %c
}
; CHECK-LABEL: test16k
; CHECK: valignq $2, %zmm0, %zmm1, %zmm2 {%k1} #
define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) nounwind {
%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
%m = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %m, <8 x i64> %c, <8 x i64> %src
ret <8 x i64> %res
}
; CHECK-LABEL: test17
; CHECK: vshufpd $19, %zmm1, %zmm0
; CHECK: ret