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Hexagon: Use multiclass for absolute addressing mode stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
294014e158
commit
691c365aad
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@ -4040,143 +4040,111 @@ let isReturn = 1, isTerminator = 1,
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Requires<[HasV4T]>;
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}
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// Load/Store with absolute addressing mode
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// memw(#u6)=Rt
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multiclass ST_abs<string OpcStr> {
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let isPredicable = 1 in
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def _abs_V4 : STInst2<(outs),
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(ins globaladdress:$absaddr, IntRegs:$src),
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!strconcat(OpcStr, "(##$absaddr) = $src"),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if ($src1)",
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!strconcat(OpcStr, "(##$absaddr) = $src2")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if (!$src1)",
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!strconcat(OpcStr, "(##$absaddr) = $src2")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if ($src1.new)",
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!strconcat(OpcStr, "(##$absaddr) = $src2")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if (!$src1.new)",
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!strconcat(OpcStr, "(##$absaddr) = $src2")),
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[]>,
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Requires<[HasV4T]>;
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def _abs_nv_V4 : STInst2<(outs),
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(ins globaladdress:$absaddr, IntRegs:$src),
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!strconcat(OpcStr, "(##$absaddr) = $src.new"),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cPt_nv_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if ($src1)",
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!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cNotPt_nv_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if (!$src1)",
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!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cdnPt_nv_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if ($src1.new)",
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!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
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[]>,
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Requires<[HasV4T]>;
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let isPredicated = 1 in
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def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
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!strconcat("if (!$src1.new)",
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!strconcat(OpcStr, "(##$absaddr) = $src2.new")),
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multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let PNewValue = !if(isPredNew, "new", "") in
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def NAME#_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"(##$absaddr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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}
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let AddedComplexity = 30, isPredicable = 1 in
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def STrid_abs_V4 : STInst<(outs),
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(ins globaladdress:$absaddr, DoubleRegs:$src),
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"memd(##$absaddr) = $src",
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[(store (i64 DoubleRegs:$src),
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(HexagonCONST32 tglobaladdr:$absaddr))]>,
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Requires<[HasV4T]>;
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multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
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let PredSense = !if(PredNot, "false", "true") in {
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defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
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}
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}
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let AddedComplexity = 30, isPredicated = 1 in
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def STrid_abs_cPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
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"if ($src1) memd(##$absaddr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
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multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def NAME#_V4 : STInst2<(outs),
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(ins globaladdressExt:$absaddr, RC:$src),
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mnemonic#"(##$absaddr) = $src",
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[]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 30, isPredicated = 1 in
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def STrid_abs_cNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
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"if (!$src1) memd(##$absaddr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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let opExtendable = 1, isPredicated = 1 in {
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defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
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defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
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}
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}
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}
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let AddedComplexity = 30, isPredicated = 1 in
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def STrid_abs_cdnPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
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"if ($src1.new) memd(##$absaddr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let PNewValue = !if(isPredNew, "new", "") in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, globaladdressExt:$absaddr, RC: $src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"(##$absaddr) = $src2.new",
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[]>,
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Requires<[HasV4T]>;
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}
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let AddedComplexity = 30, isPredicated = 1 in
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def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
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(ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
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"if (!$src1.new) memd(##$absaddr) = $src2",
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[]>,
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Requires<[HasV4T]>;
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multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
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let PredSense = !if(PredNot, "false", "true") in {
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defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
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}
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}
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defm STrib : ST_abs<"memb">;
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defm STrih : ST_abs<"memh">;
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defm STriw : ST_abs<"memw">;
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let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
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multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins globaladdressExt:$absaddr, RC:$src),
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mnemonic#"(##$absaddr) = $src.new",
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[]>,
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Requires<[HasV4T]>;
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let Predicates = [HasV4T], AddedComplexity = 30 in
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let opExtendable = 1, isPredicated = 1 in {
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defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
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defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
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}
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}
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}
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let addrMode = Absolute in {
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defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
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ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
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defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
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ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
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defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
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ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
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let isNVStorable = 0 in
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defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 30 in {
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def : Pat<(truncstorei8 (i32 IntRegs:$src1),
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(HexagonCONST32 tglobaladdr:$absaddr)),
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(STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
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let Predicates = [HasV4T], AddedComplexity = 30 in
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def : Pat<(truncstorei16 (i32 IntRegs:$src1),
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(HexagonCONST32 tglobaladdr:$absaddr)),
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(STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
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let Predicates = [HasV4T], AddedComplexity = 30 in
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def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
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(STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
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def : Pat<(store (i64 DoubleRegs:$src1),
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(HexagonCONST32 tglobaladdr:$absaddr)),
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(STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
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}
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multiclass LD_abs<string OpcStr> {
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let isPredicable = 1 in
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46
test/CodeGen/Hexagon/absaddr-store.ll
Normal file
46
test/CodeGen/Hexagon/absaddr-store.ll
Normal file
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@ -0,0 +1,46 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate load instructions with absolute addressing mode.
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@a = external global i32
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@b = external global i8
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@c = external global i16
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@d = external global i64
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define zeroext i8 @absStoreByte() nounwind {
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; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i8* @b, align 1
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%conv = zext i8 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i8
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store i8 %conv1, i8* @b, align 1
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ret i8 %conv1
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}
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define signext i16 @absStoreHalf() nounwind {
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; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i16* @c, align 2
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%conv = sext i16 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i16
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store i16 %conv1, i16* @c, align 2
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ret i16 %conv1
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}
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define i32 @absStoreWord() nounwind {
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; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i32* @a, align 4
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%mul = mul nsw i32 100, %0
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store i32 %mul, i32* @a, align 4
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ret i32 %mul
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}
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define void @absStoreDouble() nounwind {
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; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
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entry:
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store i64 100, i64* @d, align 8
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ret void
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}
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