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Change this overloaded use of Sched::Latency to be an overloaded

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use of Sched::ILP instead, as Sched::Latency is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2011-10-24 17:55:11 +00:00
parent 334190e47e
commit 692c1d8535
2 changed files with 6 additions and 6 deletions
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8
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -2100,9 +2100,9 @@ static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
int LHeight = (int)left->getHeight() + LPenalty;
int RHeight = (int)right->getHeight() + RPenalty;
bool LStall = (!checkPref || left->SchedulingPref == Sched::Latency) &&
bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
BUHasStall(left, LHeight, SPQ);
bool RStall = (!checkPref || right->SchedulingPref == Sched::Latency) &&
bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
BUHasStall(right, RHeight, SPQ);
// If scheduling one of the node will cause a pipeline stall, delay it.
@ -2124,8 +2124,8 @@ static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
// If either node is scheduling for latency, sort them by height/depth
// and latency.
if (!checkPref || (left->SchedulingPref == Sched::Latency ||
right->SchedulingPref == Sched::Latency)) {
if (!checkPref || (left->SchedulingPref == Sched::ILP ||
right->SchedulingPref == Sched::ILP)) {
if (DisableSchedCycles) {
if (LHeight != RHeight) {
DEBUG(++FactorCount[FactHeight]);

4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -986,7 +986,7 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
if (VT == MVT::Glue || VT == MVT::Other)
continue;
if (VT.isFloatingPoint() || VT.isVector())
return Sched::Latency;
return Sched::ILP;
}
if (!N->isMachineOpcode())
@ -1001,7 +1001,7 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
return Sched::RegPressure;
if (!Itins->isEmpty() &&
Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
return Sched::Latency;
return Sched::ILP;
return Sched::RegPressure;
}