From 69643f47adb9b7c72b35f5b976388d17b78ae52b Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 22 Oct 2014 04:26:10 +0000
Subject: [PATCH] R600/SI: Add failing testcase reduced from OpenCV

This fails the verifier with:
"Expected a VCSrc_32 register, but got a VReg_1 register"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220368 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/R600/v-cmp-vreg1-src-error.ll | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 test/CodeGen/R600/v-cmp-vreg1-src-error.ll

diff --git a/test/CodeGen/R600/v-cmp-vreg1-src-error.ll b/test/CodeGen/R600/v-cmp-vreg1-src-error.ll
new file mode 100644
index 00000000000..3892c9bad34
--- /dev/null
+++ b/test/CodeGen/R600/v-cmp-vreg1-src-error.ll
@@ -0,0 +1,22 @@
+; XFAIL: *
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s
+
+define void @init_data_cost_reduce_0(i32 %arg) #0 {
+bb:
+  br i1 undef, label %bb1, label %bb2
+
+bb1:                                              ; preds = %bb
+  br label %bb2
+
+bb2:                                              ; preds = %bb1, %bb
+  br i1 undef, label %bb3, label %bb4
+
+bb3:                                              ; preds = %bb2
+  %tmp = mul i32 undef, %arg
+  br label %bb4
+
+bb4:                                              ; preds = %bb3, %bb2
+  unreachable
+}
+
+attributes #0 = { nounwind }