mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
[X86][SSE] Vectorized i64 uniform constant SRA shifts
This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
610992baca
commit
6970be03d1
@ -1032,6 +1032,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SHL, MVT::v2i64, Custom);
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setOperationAction(ISD::SHL, MVT::v4i32, Custom);
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setOperationAction(ISD::SRA, MVT::v2i64, Custom);
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setOperationAction(ISD::SRA, MVT::v4i32, Custom);
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}
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@ -1211,6 +1212,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SHL, MVT::v4i64, Custom);
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setOperationAction(ISD::SHL, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v4i64, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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// Custom lower several nodes for 256-bit types.
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@ -16948,6 +16950,38 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
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(Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
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auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
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assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
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MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
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SDValue Ex = DAG.getBitcast(ExVT, R);
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if (ShiftAmt >= 32) {
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// Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
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SDValue Upper =
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getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
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SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
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ShiftAmt - 32, DAG);
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if (VT == MVT::v2i64)
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Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
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if (VT == MVT::v4i64)
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Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
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{9, 1, 11, 3, 13, 5, 15, 7});
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} else {
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// SRA upper i32, SHL whole i64 and select lower i32.
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SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
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ShiftAmt, DAG);
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SDValue Lower =
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getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
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Lower = DAG.getBitcast(ExVT, Lower);
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if (VT == MVT::v2i64)
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Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
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if (VT == MVT::v4i64)
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Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
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{8, 1, 10, 3, 12, 5, 14, 7});
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}
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return DAG.getBitcast(VT, Ex);
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};
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// Optimize shl/srl/sra with constant shift amount.
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if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
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if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
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@ -16956,6 +16990,11 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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// i64 SRA needs to be performed as partial shifts.
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if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
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Op.getOpcode() == ISD::SRA)
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return ArithmeticShiftRight64(ShiftAmt);
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if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
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unsigned NumElts = VT.getVectorNumElements();
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MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
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@ -17039,7 +17078,12 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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if (ShAmt != ShiftAmt)
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return SDValue();
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}
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
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return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
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if (Op.getOpcode() == ISD::SRA)
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return ArithmeticShiftRight64(ShiftAmt);
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}
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return SDValue();
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@ -17121,7 +17165,9 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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if (Vals[j] != Amt.getOperand(i + j))
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return SDValue();
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}
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return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
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if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
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return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
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}
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return SDValue();
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}
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@ -117,6 +117,8 @@ unsigned X86TTIImpl::getArithmeticInstrCost(
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static const CostTblEntry<MVT::SimpleValueType>
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AVX2UniformConstCostTable[] = {
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{ ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
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{ ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
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{ ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
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{ ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
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@ -211,6 +213,7 @@ unsigned X86TTIImpl::getArithmeticInstrCost(
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{ ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
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{ ISD::SRA, MVT::v8i16, 1 }, // psraw.
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{ ISD::SRA, MVT::v4i32, 1 }, // psrad.
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{ ISD::SRA, MVT::v2i64, 4 }, // 2 x psrad + shuffle.
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{ ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
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{ ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
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@ -247,9 +247,9 @@ entry:
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define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) {
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entry:
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; SSE2: shift2i16const
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; SSE2: cost of 20 {{.*}} ashr
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; SSE2: cost of 4 {{.*}} ashr
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; SSE2-CODEGEN: shift2i16const
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; SSE2-CODEGEN: sarq $
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec %a , <i16 3, i16 3>
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ret %shifttypec %0
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@ -320,9 +320,9 @@ entry:
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define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) {
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entry:
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; SSE2: shift2i32c
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; SSE2: cost of 20 {{.*}} ashr
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; SSE2: cost of 4 {{.*}} ashr
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; SSE2-CODEGEN: shift2i32c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec2i32 %a , <i32 3, i32 3>
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ret %shifttypec2i32 %0
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@ -391,9 +391,9 @@ entry:
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define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) {
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entry:
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; SSE2: shift2i64c
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; SSE2: cost of 20 {{.*}} ashr
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; SSE2: cost of 4 {{.*}} ashr
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; SSE2-CODEGEN: shift2i64c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec2i64 %a , <i64 3, i64 3>
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ret %shifttypec2i64 %0
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@ -403,9 +403,9 @@ entry:
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define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) {
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entry:
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; SSE2: shift4i64c
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; SSE2: cost of 40 {{.*}} ashr
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; SSE2: cost of 8 {{.*}} ashr
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; SSE2-CODEGEN: shift4i64c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec4i64 %a , <i64 3, i64 3, i64 3, i64 3>
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ret %shifttypec4i64 %0
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@ -415,9 +415,9 @@ entry:
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define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) {
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entry:
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; SSE2: shift8i64c
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; SSE2: cost of 80 {{.*}} ashr
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; SSE2: cost of 16 {{.*}} ashr
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; SSE2-CODEGEN: shift8i64c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec8i64 %a , <i64 3, i64 3, i64 3, i64 3,
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i64 3, i64 3, i64 3, i64 3>
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@ -428,9 +428,9 @@ entry:
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define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) {
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entry:
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; SSE2: shift16i64c
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; SSE2: cost of 160 {{.*}} ashr
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; SSE2: cost of 32 {{.*}} ashr
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; SSE2-CODEGEN: shift16i64c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec16i64 %a , <i64 3, i64 3, i64 3, i64 3,
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i64 3, i64 3, i64 3, i64 3,
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@ -443,9 +443,9 @@ entry:
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define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) {
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entry:
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; SSE2: shift32i64c
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; SSE2: cost of 320 {{.*}} ashr
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; SSE2: cost of 64 {{.*}} ashr
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; SSE2-CODEGEN: shift32i64c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec32i64 %a ,<i64 3, i64 3, i64 3, i64 3,
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i64 3, i64 3, i64 3, i64 3,
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@ -462,9 +462,9 @@ entry:
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define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) {
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entry:
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; SSE2: shift2i8c
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; SSE2: cost of 20 {{.*}} ashr
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; SSE2: cost of 4 {{.*}} ashr
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; SSE2-CODEGEN: shift2i8c
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; SSE2-CODEGEN: sarq $3
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; SSE2-CODEGEN: psrad $3
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%0 = ashr %shifttypec2i8 %a , <i8 3, i8 3>
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ret %shifttypec2i8 %0
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@ -954,38 +954,35 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
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define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
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; SSE2-LABEL: splatconstant_shift_v2i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: sarq $7, %rax
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; SSE2-NEXT: movd %rax, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: sarq $7, %rax
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; SSE2-NEXT: movd %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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; SSE2-NEXT: psrad $7, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
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; SSE2-NEXT: psrlq $7, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: splatconstant_shift_v2i64:
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; SSE41: # BB#0:
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; SSE41-NEXT: pextrq $1, %xmm0, %rax
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; SSE41-NEXT: sarq $7, %rax
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; SSE41-NEXT: movd %rax, %xmm1
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; SSE41-NEXT: movd %xmm0, %rax
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; SSE41-NEXT: sarq $7, %rax
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; SSE41-NEXT: movd %rax, %xmm0
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE41-NEXT: movdqa %xmm0, %xmm1
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; SSE41-NEXT: psrad $7, %xmm1
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; SSE41-NEXT: psrlq $7, %xmm0
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: splatconstant_shift_v2i64:
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; AVX: # BB#0:
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; AVX-NEXT: vpextrq $1, %xmm0, %rax
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; AVX-NEXT: sarq $7, %rax
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; AVX-NEXT: vmovq %rax, %xmm1
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; AVX-NEXT: vmovq %xmm0, %rax
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; AVX-NEXT: sarq $7, %rax
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; AVX-NEXT: vmovq %rax, %xmm0
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; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: retq
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; AVX1-LABEL: splatconstant_shift_v2i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpsrad $7, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: splatconstant_shift_v2i64:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsrad $7, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlq $7, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
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; AVX2-NEXT: retq
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%shift = ashr <2 x i64> %a, <i64 7, i64 7>
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ret <2 x i64> %shift
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}
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@ -663,41 +663,20 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
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; AVX1-LABEL: splatconstant_shift_v4i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpextrq $1, %xmm1, %rax
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; AVX1-NEXT: sarq $7, %rax
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; AVX1-NEXT: vmovq %rax, %xmm2
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; AVX1-NEXT: vmovq %xmm1, %rax
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; AVX1-NEXT: sarq $7, %rax
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; AVX1-NEXT: vmovq %rax, %xmm1
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; AVX1-NEXT: vpextrq $1, %xmm0, %rax
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; AVX1-NEXT: sarq $7, %rax
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; AVX1-NEXT: vmovq %rax, %xmm2
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; AVX1-NEXT: vmovq %xmm0, %rax
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; AVX1-NEXT: sarq $7, %rax
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; AVX1-NEXT: vmovq %rax, %xmm0
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vpsrad $7, %xmm1, %xmm2
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; AVX1-NEXT: vpsrlq $7, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpsrad $7, %xmm0, %xmm2
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; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: splatconstant_shift_v4i64:
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; AVX2: # BB#0:
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpextrq $1, %xmm1, %rax
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; AVX2-NEXT: sarq $7, %rax
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; AVX2-NEXT: vmovq %rax, %xmm2
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; AVX2-NEXT: vmovq %xmm1, %rax
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; AVX2-NEXT: sarq $7, %rax
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; AVX2-NEXT: vmovq %rax, %xmm1
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; AVX2-NEXT: vpextrq $1, %xmm0, %rax
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; AVX2-NEXT: sarq $7, %rax
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; AVX2-NEXT: vmovq %rax, %xmm2
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; AVX2-NEXT: vmovq %xmm0, %rax
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; AVX2-NEXT: sarq $7, %rax
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; AVX2-NEXT: vmovq %rax, %xmm0
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX2-NEXT: vpsrad $7, %ymm0, %ymm1
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; AVX2-NEXT: vpsrlq $7, %ymm0, %ymm0
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
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; AVX2-NEXT: retq
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%shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
|
||||
ret <4 x i64> %shift
|
||||
|
||||
@ -3,13 +3,12 @@
|
||||
; test vector shifts converted to proper SSE2 vector shifts when the shift
|
||||
; amounts are the same.
|
||||
|
||||
; Note that x86 does have ashr
|
||||
; Note that x86 does have ashr
|
||||
|
||||
; shift1a can't use a packed shift
|
||||
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: shift1a:
|
||||
; CHECK: sarl
|
||||
; CHECK: psrad $31
|
||||
%ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
|
||||
store <2 x i64> %ashr, <2 x i64>* %dst
|
||||
ret void
|
||||
|
||||
@ -1,8 +1,9 @@
|
||||
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
|
||||
; CHECK: {{cwtl|movswl}}
|
||||
; CHECK: {{cwtl|movswl}}
|
||||
; CHECK: psllq $48, %xmm0
|
||||
; CHECK: psrad $16, %xmm0
|
||||
; CHECK: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
|
||||
|
||||
; sign extension v2i32 to v2i16
|
||||
; sign extension v2i16 to v2i32
|
||||
|
||||
define void @convert(<2 x i32>* %dst.addr, <2 x i16> %src) nounwind {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user