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[AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin
parent
97577757c6
commit
69b2447b6a
@ -5289,21 +5289,6 @@ def neon_uimm4 : Operand<i64>,
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let PrintMethod = "printUImmHexOperand";
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}
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class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
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RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
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: NeonI_copy<0b1, 0b0, 0b0011,
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(outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
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asmop # "\t$Rd." # Res # "[$Imm], $Rn",
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[(set (ResTy VPR128:$Rd),
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(ResTy (vector_insert
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(ResTy VPR128:$src),
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(OpTy OpGPR:$Rn),
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(OpImm:$Imm))))],
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NoItinerary> {
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bits<4> Imm;
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let Constraints = "$src = $Rd";
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}
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// Bitwise Extract
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class NeonI_Extract<bit q, bits<2> op2, string asmop,
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string OpS, RegisterOperand OpVPR, Operand OpImm>
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@ -6157,6 +6142,21 @@ defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
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// End of implementation for instruction class (3V Elem)
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class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
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RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
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: NeonI_copy<0b1, 0b0, 0b0011,
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(outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
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asmop # "\t$Rd." # Res # "[$Imm], $Rn",
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[(set (ResTy VPR128:$Rd),
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(ResTy (vector_insert
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(ResTy VPR128:$src),
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(OpTy OpGPR:$Rn),
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(OpImm:$Imm))))],
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NoItinerary> {
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bits<4> Imm;
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let Constraints = "$src = $Rd";
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}
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//Insert element (vector, from main)
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def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
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neon_uimm4_bare> {
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@ -6175,6 +6175,15 @@ def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
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let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
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}
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def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
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(INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
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def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
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(INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
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def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
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(INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
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def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
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(INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
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class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
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RegisterClass OpGPR, ValueType OpTy,
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Operand OpImm, Instruction INS>
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@ -6214,20 +6223,33 @@ def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
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}
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def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
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let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
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let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
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// bit 11 is unspecified.
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let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
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// bit 11 is unspecified, but should be set to zero.
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}
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def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
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let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
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let Inst{14-13} = {Immn{1}, Immn{0}};
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// bits 11-12 are unspecified.
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let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
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// bits 11-12 are unspecified, but should be set to zero.
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}
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def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
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let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
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let Inst{14} = Immn{0};
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// bits 11-13 are unspecified.
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let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
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// bits 11-13 are unspecified, but should be set to zero.
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}
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def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
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(INSELb VPR128:$Rd, VPR128:$Rn,
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neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
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def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
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(INSELh VPR128:$Rd, VPR128:$Rn,
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neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
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def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
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(INSELs VPR128:$Rd, VPR128:$Rn,
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neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
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def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
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(INSELd VPR128:$Rd, VPR128:$Rn,
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neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
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multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
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ValueType MidTy, Operand StImm, Operand NaImm,
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Instruction INS> {
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@ -6448,6 +6470,11 @@ def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
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let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
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}
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def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
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(UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
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def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
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(UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
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class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
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Operand StImm, Operand NaImm,
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Instruction SMOVI>
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@ -6650,37 +6677,38 @@ class NeonI_DUP<bit Q, string asmop, string rdlane,
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NoItinerary>;
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def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
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let Inst{16} = 0b1;
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// bits 17-19 are unspecified.
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let Inst{20-16} = 0b00001;
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// bits 17-20 are unspecified, but should be set to zero.
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}
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def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
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let Inst{17-16} = 0b10;
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// bits 18-19 are unspecified.
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let Inst{20-16} = 0b00010;
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// bits 18-20 are unspecified, but should be set to zero.
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}
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def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
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let Inst{18-16} = 0b100;
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// bit 19 is unspecified.
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let Inst{20-16} = 0b00100;
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// bits 19-20 are unspecified, but should be set to zero.
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}
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def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
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let Inst{19-16} = 0b1000;
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let Inst{20-16} = 0b01000;
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// bit 20 is unspecified, but should be set to zero.
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}
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def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
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let Inst{16} = 0b1;
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// bits 17-19 are unspecified.
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let Inst{20-16} = 0b00001;
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// bits 17-20 are unspecified, but should be set to zero.
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}
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def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
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let Inst{17-16} = 0b10;
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// bits 18-19 are unspecified.
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let Inst{20-16} = 0b00010;
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// bits 18-20 are unspecified, but should be set to zero.
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}
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def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
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let Inst{18-16} = 0b100;
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// bit 19 is unspecified.
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let Inst{20-16} = 0b00100;
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// bits 19-20 are unspecified, but should be set to zero.
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}
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// patterns for CONCAT_VECTORS
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@ -11,11 +11,21 @@
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ins v20.s[0], w30
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ins v1.d[1], x7
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mov v2.b[2], w1
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mov v7.h[7], w14
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mov v20.s[0], w30
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mov v1.d[1], x7
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// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e]
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// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e]
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// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e]
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// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e]
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// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e]
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// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e]
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// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e]
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// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e]
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//------------------------------------------------------------------------------
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// Signed integer move (main, from element)
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@ -30,7 +40,7 @@
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// CHECK: smov w14, v6.h[4] // encoding: [0xce,0x2c,0x12,0x0e]
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// CHECK: smov x1, v0.b[15] // encoding: [0x01,0x2c,0x1f,0x4e]
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// CHECK: smov x14, v6.h[4] // encoding: [0xce,0x2c,0x12,0x4e]
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// CHECK: smov x20, v9.s[2] // encoding: [0x34,0x2d,0x14,0x4e]
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// CHECK: smov x20, v9.s[2] // encoding: [0x34,0x2d,0x14,0x4e]
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//------------------------------------------------------------------------------
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@ -41,25 +51,41 @@
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umov w20, v9.s[2]
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umov x7, v18.d[1]
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mov w20, v9.s[2]
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mov x7, v18.d[1]
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// CHECK: umov w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e]
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// CHECK: umov w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e]
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// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e]
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// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e]
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// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e]
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// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e]
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//------------------------------------------------------------------------------
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// Insert element (vector, from element)
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//------------------------------------------------------------------------------
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Ins v1.b[14], v3.b[6]
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Ins v6.h[7], v7.h[5]
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Ins v15.s[3], v22.s[2]
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Ins v0.d[0], v4.d[1]
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ins v1.b[14], v3.b[6]
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ins v6.h[7], v7.h[5]
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ins v15.s[3], v22.s[2]
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ins v0.d[0], v4.d[1]
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mov v1.b[14], v3.b[6]
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mov v6.h[7], v7.h[5]
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mov v15.s[3], v22.s[2]
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mov v0.d[0], v4.d[1]
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// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e]
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// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e]
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// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x5e,0x1c,0x6e]
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// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e]
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// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e]
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// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e]
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// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e]
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// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e]
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// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e]
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//------------------------------------------------------------------------------
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// Duplicate to all lanes( vector, from element)
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//------------------------------------------------------------------------------
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@ -91,11 +117,11 @@
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dup v5.2d, x0
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// CHECK: dup v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e]
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// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x0a,0x0e]
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// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x14,0x0e]
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// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e]
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// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e]
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// CHECK: dup v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e]
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// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x0a,0x4e]
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// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x14,0x4e]
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// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e]
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// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e]
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// CHECK: dup v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e]
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