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Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13693,6 +13693,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
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case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
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case X86ISD::BLSR: return "X86ISD::BLSR";
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case X86ISD::BLSR: return "X86ISD::BLSR";
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case X86ISD::BZHI: return "X86ISD::BZHI";
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case X86ISD::BZHI: return "X86ISD::BZHI";
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case X86ISD::BEXTR: return "X86ISD::BEXTR";
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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case X86ISD::PTEST: return "X86ISD::PTEST";
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case X86ISD::PTEST: return "X86ISD::PTEST";
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case X86ISD::TESTP: return "X86ISD::TESTP";
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case X86ISD::TESTP: return "X86ISD::TESTP";
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@ -17503,6 +17504,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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// BLSI is X & (-X)
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// BLSI is X & (-X)
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// BLSR is X & (X-1)
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// BLSR is X & (X-1)
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// BZHI is X & ((1 << Y) - 1)
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// BZHI is X & ((1 << Y) - 1)
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// BEXTR is ((X >> imm) & (2**size-1))
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if (VT == MVT::i32 || VT == MVT::i64) {
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if (VT == MVT::i32 || VT == MVT::i64) {
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SDValue N0 = N->getOperand(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N1 = N->getOperand(1);
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@ -17528,6 +17530,22 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
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if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
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isAllOnes(N1.getOperand(1)))
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isAllOnes(N1.getOperand(1)))
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return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
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return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
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// Check for BEXTR
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if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) {
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ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
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if (MaskNode && ShiftNode) {
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uint64_t Mask = MaskNode->getZExtValue();
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uint64_t Shift = ShiftNode->getZExtValue();
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if (isMask_64(Mask)) {
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uint64_t MaskSize = CountPopulation_64(Mask);
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if (Shift + MaskSize <= VT.getSizeInBits())
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return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
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DAG.getConstant(Shift | (MaskSize << 8), VT));
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}
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}
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}
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}
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}
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if (Subtarget->hasBMI2()) {
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if (Subtarget->hasBMI2()) {
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@ -296,6 +296,7 @@ namespace llvm {
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BLSMSK, // BLSMSK - Get mask up to lowest set bit
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BLSMSK, // BLSMSK - Get mask up to lowest set bit
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BLSR, // BLSR - Reset lowest set bit
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BLSR, // BLSR - Reset lowest set bit
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BZHI, // BZHI - Zero high bits
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BZHI, // BZHI - Zero high bits
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BEXTR, // BEXTR - Bit field extract
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UMUL, // LOW, HI, FLAGS = umul LHS, RHS
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UMUL, // LOW, HI, FLAGS = umul LHS, RHS
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@ -253,6 +253,7 @@ def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
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def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
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def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
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def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
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def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
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def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
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def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
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def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntShiftOp>;
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def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
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def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
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@ -1869,6 +1870,15 @@ def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
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(BZHI64rm addr:$src1,
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(BZHI64rm addr:$src1,
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(X86bextr GR32:$src1, GR32:$src2),
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(BEXTR32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
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(BEXTR32rm addr:$src1, GR32:$src2)>;
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def : Pat<(X86bextr GR64:$src1, GR64:$src2),
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(BEXTR64rr GR64:$src1, GR64:$src2)>;
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def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
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(BEXTR64rm addr:$src1, GR64:$src2)>;
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multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
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multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic Int,
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X86MemOperand x86memop, Intrinsic Int,
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PatFrag ld_frag> {
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PatFrag ld_frag> {
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@ -111,6 +111,23 @@ define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone {
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
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define i32 @bextr32b(i32 %x) nounwind uwtable readnone ssp {
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%1 = lshr i32 %x, 4
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%2 = and i32 %1, 4095
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ret i32 %2
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; CHECK-LABEL: bextr32b:
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; CHECK: bextrl
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}
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define i32 @bextr32b_load(i32* %x) nounwind uwtable readnone ssp {
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%1 = load i32* %x
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%2 = lshr i32 %1, 4
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%3 = and i32 %2, 4095
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ret i32 %3
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; CHECK-LABEL: bextr32b_load:
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; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
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}
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define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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ret i64 %tmp
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ret i64 %tmp
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@ -120,6 +137,14 @@ define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
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define i64 @bextr64b(i64 %x) nounwind uwtable readnone ssp {
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%1 = lshr i64 %x, 4
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%2 = and i64 %1, 4095
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ret i64 %2
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; CHECK-LABEL: bextr64b:
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; CHECK: bextrq
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}
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define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
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define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
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ret i32 %tmp
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ret i32 %tmp
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