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Add support for marking each operand as a %hh, %hm, %lm or %lo.
Represent previous bools and these ones with flags in a single byte per operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2863 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,6 +64,15 @@ public:
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MO_PCRelativeDisp,
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MO_PCRelativeDisp,
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};
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};
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private:
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// Bit fields of the flags variable used for different operand properties
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static const char DEFFLAG = 0x1; // this is a def of the operand
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static const char DEFUSEFLAG = 0x2; // this is both a def and a use
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static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
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static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
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static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
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static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
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private:
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private:
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MachineOperandType opType;
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MachineOperandType opType;
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@ -78,9 +87,8 @@ private:
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int regNum; // register number for an explicit register
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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// will be set for a value after reg allocation
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bool isDef; // is this a definition for the value?
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char flags; // see bit field definitions above
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bool isDefAndUse; // is this a both a def and a use of the value?
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// we assume that a non-def *must* be a use.
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public:
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public:
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/*ctor*/ MachineOperand ();
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/*ctor*/ MachineOperand ();
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/*ctor*/ MachineOperand (MachineOperandType operandType,
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/*ctor*/ MachineOperand (MachineOperandType operandType,
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@ -108,20 +116,39 @@ public:
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return immedVal;
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return immedVal;
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}
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}
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inline bool opIsDef () const {
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inline bool opIsDef () const {
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return isDef;
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return flags & DEFFLAG;
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}
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}
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inline bool opIsDefAndUse () const {
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inline bool opIsDefAndUse () const {
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return isDefAndUse;
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return flags & DEFUSEFLAG;
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}
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inline bool opHiBits32 () const {
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return flags & HIFLAG32;
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}
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inline bool opLoBits32 () const {
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return flags & LOFLAG32;
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}
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inline bool opHiBits64 () const {
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return flags & HIFLAG64;
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}
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inline bool opLoBits64 () const {
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return flags & LOFLAG64;
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}
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// used to get the reg number if when one is allocated (must be
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// called only after reg alloc)
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inline int getAllocatedRegNum() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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return regNum;
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}
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}
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public:
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public:
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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private:
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private:
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// These functions are provided so that a vector of operands can be
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// These functions are provided so that a vector of operands can be
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// statically allocated and individual ones can be initialized later.
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// statically allocated and individual ones can be initialized later.
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// Give class MachineInstr gets access to these functions.
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// Give class MachineInstr access to these functions.
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//
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//
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void Initialize (MachineOperandType operandType,
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void Initialize (MachineOperandType operandType,
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Value* _val);
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Value* _val);
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@ -130,6 +157,15 @@ private:
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void InitializeReg (int regNum,
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void InitializeReg (int regNum,
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bool isCCReg);
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bool isCCReg);
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// Construction methods needed for fine-grain control.
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// These must be accessed via coresponding methods in MachineInstr.
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void markDef() { flags |= DEFFLAG; }
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void markDefAndUse() { flags |= DEFUSEFLAG; }
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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// Replaces the Value with its corresponding physical register after
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// Replaces the Value with its corresponding physical register after
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// register allocation is complete
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// register allocation is complete
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void setRegForValue(int reg) {
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void setRegForValue(int reg) {
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@ -137,18 +173,8 @@ private:
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opType == MO_MachineRegister);
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opType == MO_MachineRegister);
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regNum = reg;
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regNum = reg;
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}
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}
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friend class MachineInstr;
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public:
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// used to get the reg number if when one is allocted (must be
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friend class MachineInstr;
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// called only after reg alloc)
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inline int getAllocatedRegNum() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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return regNum;
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}
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};
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};
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@ -157,8 +183,7 @@ MachineOperand::MachineOperand()
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: opType(MO_VirtualRegister),
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: opType(MO_VirtualRegister),
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immedVal(0),
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immedVal(0),
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regNum(-1),
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regNum(-1),
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isDef(false),
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flags(0)
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isDefAndUse(false)
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{}
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{}
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inline
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inline
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@ -167,15 +192,13 @@ MachineOperand::MachineOperand(MachineOperandType operandType,
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: opType(operandType),
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: opType(operandType),
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immedVal(0),
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immedVal(0),
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regNum(-1),
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regNum(-1),
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isDef(false),
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flags(0)
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isDefAndUse(false)
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{}
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{}
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inline
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inline
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MachineOperand::MachineOperand(const MachineOperand& mo)
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MachineOperand::MachineOperand(const MachineOperand& mo)
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: opType(mo.opType),
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: opType(mo.opType),
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isDef(false),
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flags(mo.flags)
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isDefAndUse(false)
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{
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{
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switch(opType) {
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switch(opType) {
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case MO_VirtualRegister:
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case MO_VirtualRegister:
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@ -195,6 +218,7 @@ MachineOperand::Initialize(MachineOperandType operandType,
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opType = operandType;
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opType = operandType;
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value = _val;
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value = _val;
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regNum = -1;
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regNum = -1;
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flags = 0;
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}
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}
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inline void
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inline void
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@ -205,6 +229,7 @@ MachineOperand::InitializeConst(MachineOperandType operandType,
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value = NULL;
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value = NULL;
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immedVal = intValue;
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immedVal = intValue;
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regNum = -1;
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regNum = -1;
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flags = 0;
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}
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}
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inline void
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inline void
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@ -213,6 +238,7 @@ MachineOperand::InitializeReg(int _regNum, bool isCCReg)
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opType = isCCReg? MO_CCRegister : MO_MachineRegister;
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opType = isCCReg? MO_CCRegister : MO_MachineRegister;
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value = NULL;
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value = NULL;
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regNum = (int) _regNum;
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regNum = (int) _regNum;
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flags = 0;
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}
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}
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@ -330,6 +356,12 @@ public:
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Value* val,
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Value* val,
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bool isDef=false,
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bool isDef=false,
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bool isDefAndUse=false);
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bool isDefAndUse=false);
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void setOperandHi32 (unsigned i);
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void setOperandLo32 (unsigned i);
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void setOperandHi64 (unsigned i);
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void setOperandLo64 (unsigned i);
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// Replaces the Value for the operand with its allocated
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// Replaces the Value for the operand with its allocated
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// physical register after register allocation is complete.
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// physical register after register allocation is complete.
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@ -477,6 +509,30 @@ MachineInstr::setImplicitRef(unsigned int i,
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implicitIsDefAndUse[i] = isDefAndUse;
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implicitIsDefAndUse[i] = isDefAndUse;
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}
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}
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inline void
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MachineInstr::setOperandHi32(unsigned i)
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{
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operands[i].markHi32();
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}
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inline void
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MachineInstr::setOperandLo32(unsigned i)
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{
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operands[i].markLo32();
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}
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inline void
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MachineInstr::setOperandHi64(unsigned i)
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{
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operands[i].markHi64();
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}
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inline void
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MachineInstr::setOperandLo64(unsigned i)
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{
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operands[i].markLo64();
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}
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Debugging Support
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// Debugging Support
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