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Hooks for predication support.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-23 07:22:05 +00:00
parent d90733035d
commit 69d555611a
2 changed files with 39 additions and 9 deletions
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41
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -298,11 +298,6 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
return NewMIs[0]; return NewMIs[0];
} }
static bool isPredicated(MachineInstr *MI) {
MachineOperand *PMO = MI->findFirstPredOperand();
return PMO && PMO->getImmedValue() != ARMCC::AL;
}
// Branch analysis. // Branch analysis.
bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
@ -436,23 +431,53 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return false; return false;
} }
bool ARMInstrInfo::isPredicated(MachineInstr *MI) const {
MachineOperand *PMO = MI->findFirstPredOperand();
return PMO && PMO->getImmedValue() != ARMCC::AL;
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI, bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const { std::vector<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) { if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc)); MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
MI->addImmOperand(Cond[0].getImmedValue()); MI->addImmOperand(Pred[0].getImmedValue());
return true; return true;
} }
MachineOperand *PMO = MI->findFirstPredOperand(); MachineOperand *PMO = MI->findFirstPredOperand();
if (PMO) { if (PMO) {
PMO->setImm(Cond[0].getImmedValue()); PMO->setImm(Pred[0].getImmedValue());
return true; return true;
} }
return false; return false;
} }
bool ARMInstrInfo::SubsumesPredicate(std::vector<MachineOperand> &Pred1,
std::vector<MachineOperand> &Pred2) const{
if (Pred1.size() > 1 || Pred2.size() > 1)
return false;
ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
if (CC1 == CC2)
return true;
switch (CC1) {
default:
return false;
case ARMCC::AL:
return true;
case ARMCC::HS:
return CC2 == ARMCC::HI || CC2 == ARMCC::EQ;
case ARMCC::LS:
return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
case ARMCC::GE:
return CC2 == ARMCC::GT || CC2 == ARMCC::EQ;
case ARMCC::LE: return "le";
return CC2 == ARMCC::LT || CC2 == ARMCC::EQ;
}
}
/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,

7
lib/Target/ARM/ARMInstrInfo.h
View File

@ -104,8 +104,13 @@ public:
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
// Predication support. // Predication support.
virtual bool isPredicated(MachineInstr *MI) const;
virtual bool PredicateInstruction(MachineInstr *MI, virtual bool PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const; std::vector<MachineOperand> &Pred) const;
virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
std::vector<MachineOperand> &Pred1) const;
}; };
// Utility routines // Utility routines