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Some instructions are passed to the assembler to be
transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,33 +58,37 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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// Direct object specific instruction lowering
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if (!OutStreamer.hasRawTextSupport())
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switch (MI->getOpcode()) {
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case Mips::DSLL:
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case Mips::DSRL:
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case Mips::DSRA:
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assert(MI->getNumOperands() == 3 &&
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"Invalid no. of machine operands for shift!");
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assert(MI->getOperand(2).isImm());
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int64_t Shift = MI->getOperand(2).getImm();
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if (Shift > 31) {
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MCInst TmpInst0;
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MCInstLowering.LowerLargeShift(MI, TmpInst0, Shift - 32);
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OutStreamer.EmitInstruction(TmpInst0);
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return;
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}
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break;
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}
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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MCInst TmpInst0;
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// Direct object specific instruction lowering
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if (!OutStreamer.hasRawTextSupport())
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switch (I->getOpcode()) {
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// If shift amount is >= 32 it the inst needs to be lowered further
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case Mips::DSLL:
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case Mips::DSRL:
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case Mips::DSRA:
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{
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assert(I->getNumOperands() == 3 &&
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"Invalid no. of machine operands for shift!");
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assert(I->getOperand(2).isImm());
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int64_t Shift = I->getOperand(2).getImm();
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if (Shift > 31) {
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MCInst TmpInst0;
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MCInstLowering.LowerLargeShift(I, TmpInst0, Shift - 32);
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OutStreamer.EmitInstruction(TmpInst0);
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return;
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}
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}
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}
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MCInstLowering.Lower(I++, TmpInst0);
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OutStreamer.EmitInstruction(TmpInst0);
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} while ((I != E) && I->isInsideBundle());
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} while ((I != E) && I->isInsideBundle()); // Delay slot check
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}
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//===----------------------------------------------------------------------===//
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@ -1,5 +1,8 @@
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; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
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; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
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; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
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; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
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; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
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define i64 @f3(i64 %a0) nounwind readnone {
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entry:
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