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Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.

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Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-06 01:18:32 +00:00
parent 3bfe57e123
commit 6a1220eeca
2 changed files with 7 additions and 8 deletions
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10
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -547,7 +547,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
return false;
case ARM::SMLAL: case ARM::SMULL: case ARM::UMAAL: case ARM::UMLAL:
case ARM::UMULL: case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB:
case ARM::SMLALTT: case ARM::SMLSLD:
case ARM::SMLALTT: case ARM::SMLSLD: case ARM::SMLSLDX:
if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
return true;
if (R19_16 == R15_12)
@ -1201,12 +1201,8 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
}
OpIdx += 1;
} else {
// The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of
// A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1,
// we should reject this insn as invalid.
//
// Ditto for LDRBT.
if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1))
// If Inst{25} = 1 and Inst{4} != 0, we should reject this as invalid.
if (slice(insn,4,4) == 1)
return false;
// Disassemble the offset reg (Rm), shift type, and immediate shift length.