6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-25 16:29:20 +00:00
Code Issues Projects Releases Wiki Activity

Handle a v2f64 formal parameter that is split between registers and memory

Browse Source 
such that the entire second half is in memory.  Radar 7855014.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-04-13 22:03:22 +00:00
parent 535f4de469
commit 6a234f07fa
2 changed files with 20 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1613,10 +1613,8 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue ArgValue2;
if (NextVA.isMemLoc()) {
unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
MachineFrameInfo *MFI = MF.getFrameInfo();
int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset(),
true, false);
int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
// Create load node to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
@ -1665,14 +1663,22 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
if (VA.needsCustom()) {
// f64 and vector types are split up into multiple registers or
// combinations of registers and stack slots.
RegVT = MVT::i32;
if (VA.getLocVT() == MVT::v2f64) {
SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
VA = ArgLocs[++i]; // skip ahead to next loc
SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
SDValue ArgValue2;
if (VA.isMemLoc()) {
int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
true, false);
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0,
false, false, 0);
} else {
ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
}
ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
ArgValue, ArgValue1, DAG.getIntPtrConstant(0));

7
test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll Normal file
View File

@ -0,0 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8
; Radar 7855014
define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind {
entry:
unreachable
}