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stop pattern matching 16-bit zero's of a register to MOV16r0,

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instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-12-23 01:30:26 +00:00
parent 0d58013c3f
commit 6a38182471
1 changed files with 10 additions and 4 deletions
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14
lib/Target/X86/X86InstrInfo.td
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@ -3700,15 +3700,21 @@ let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
"xor{b}\t$dst, $dst",
[(set GR8:$dst, 0)]>;
def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
"xor{l}\t$dst, $dst",
[(set GR32:$dst, 0)]>;
// Use xorl instead of xorw since we don't care about the high 16 bits,
// it's smaller, and it avoids a partial-register update.
def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
"", [(set GR16:$dst, 0)]>;
def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
"xor{l}\t$dst, $dst",
[(set GR32:$dst, 0)]>;
"", [/*(set GR16:$dst, 0)*/]>;
}
let AddedComplexity = 1 in
def : Pat<(i16 0),
(EXTRACT_SUBREG (MOV32r0), x86_subreg_16bit)>;
//===----------------------------------------------------------------------===//
// Thread Local Storage Instructions
//