6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-30 20:24:32 +00:00
Code Issues Projects Releases Wiki Activity

Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl

Browse Source 
in order to fold it into a load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2010-11-09 01:54:35 +00:00
parent be7c5116a7
commit 6a559cd695
2 changed files with 39 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4120,6 +4120,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// we can fold the truncate through the shift. // we can fold the truncate through the shift.
unsigned ShLeftAmt = 0; unsigned ShLeftAmt = 0;
if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
ExtVT == VT &&
TLI.isNarrowingProfitable(N0.getValueType(), VT)) { TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
ShLeftAmt = N01->getZExtValue(); ShLeftAmt = N01->getZExtValue();

43
test/CodeGen/X86/narrow-shl-load.ll
View File

@ -1,12 +1,11 @@
; RUN: llc -march=x86-64 < %s ; RUN: llc -march=x86-64 < %s | FileCheck %s
; DAGCombiner should fold this code in finite time.
; rdar://8606584
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-pc-linux-gnu" target triple = "x86_64-pc-linux-gnu"
; DAGCombiner should fold this code in finite time.
; rdar://8606584
define void @D() nounwind readnone { define void @D() nounwind readnone {
bb.nph: bb.nph:
br label %while.cond br label %while.cond
@ -30,3 +29,37 @@ while.cond: ; preds = %while.cond, %bb.nph
while.end: ; preds = %while.cond while.end: ; preds = %while.cond
ret void ret void
} }
; DAGCombiner shouldn't fold the sdiv (ashr) away.
; rdar://8636812
; CHECK: main:
; CHECK: sarl
define i32 @main() nounwind {
entry:
%i = alloca i32, align 4
%j = alloca i8, align 1
store i32 127, i32* %i, align 4
store i8 0, i8* %j, align 1
%tmp3 = load i32* %i, align 4
%mul = mul nsw i32 %tmp3, 2
%conv4 = trunc i32 %mul to i8
%conv5 = sext i8 %conv4 to i32
%div6 = sdiv i32 %conv5, 2
%conv7 = trunc i32 %div6 to i8
%conv9 = sext i8 %conv7 to i32
%cmp = icmp eq i32 %conv9, -1
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
ret i32 0
if.end: ; preds = %entry
call void @abort() noreturn
unreachable
}
declare void @abort() noreturn
declare void @exit(i32) noreturn