Add the majority of the vector machien value types we expect to support,

and make a few changes to the legalization machinery to support more than
16 types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-11-29 05:45:29 +00:00
parent 5ee16ea417
commit 6a648614e8
7 changed files with 42 additions and 12 deletions

View File

@ -48,14 +48,26 @@ namespace MVT { // MVT = Machine Value Types
// be refined into a target vector type, or
// scalarized.
// These are 128 bit vectors of varying packed types
v16i8 = 14, // 16 x i8
v8i16 = 15, // 8 x i16
v4i32 = 16, // 4 x i32
v2i64 = 17, // 2 x i64
v4f32 = 18, // 4 x f32
v2f64 = 19, // 2 x f64
LAST_VALUETYPE, // This always remains at the end of the list.
};
static inline bool isInteger(ValueType VT) {
return VT >= i1 && VT <= i128;
return (VT >= i1 && VT <= i128) || (VT >= v16i8 && VT <= v2i64);
}
static inline bool isFloatingPoint(ValueType VT) {
return VT >= f32 && VT <= f128;
return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
}
static inline bool isVector(ValueType VT) {
return (VT >= v16i8 && VT <= v2f64);
}
static inline unsigned getSizeInBits(ValueType VT) {
@ -70,7 +82,13 @@ namespace MVT { // MVT = Machine Value Types
case MVT::i64 : return 64;
case MVT::f80 : return 80;
case MVT::f128:
case MVT::i128: return 128;
case MVT::i128:
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64: return 128;
}
}

View File

@ -123,7 +123,7 @@ public:
LegalizeAction getTypeAction(MVT::ValueType VT) const {
return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
}
unsigned getValueTypeActions() const { return ValueTypeActions; }
unsigned long long getValueTypeActions() const { return ValueTypeActions; }
/// getTypeToTransformTo - For types supported by the target, this is an
/// identity function. For types that must be promoted to larger types, this
@ -441,7 +441,7 @@ private:
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
unsigned ValueTypeActions;
unsigned long long ValueTypeActions;
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this

View File

@ -52,7 +52,7 @@ class SelectionDAGLegalize {
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
unsigned ValueTypeActions;
unsigned long long ValueTypeActions;
/// NeedsAnotherIteration - This is set when we expand a large integer
/// operation into smaller integer operations, but the smaller operations are
@ -161,7 +161,7 @@ static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
ValueTypeActions(TLI.getValueTypeActions()) {
assert(MVT::LAST_VALUETYPE <= 16 &&
assert(MVT::LAST_VALUETYPE <= 32 &&
"Too many value types for ValueTypeActions to hold!");
}

View File

@ -42,8 +42,8 @@ static void SetValueTypeAction(MVT::ValueType VT,
TargetLowering::LegalizeAction Action,
TargetLowering &TLI,
MVT::ValueType *TransformToType,
unsigned &ValueTypeActions) {
ValueTypeActions |= Action << (VT*2);
unsigned long long &ValueTypeActions) {
ValueTypeActions |= (unsigned long long)Action << (VT*2);
if (Action == TargetLowering::Promote) {
MVT::ValueType PromoteTo;
if (VT == MVT::f32)
@ -75,7 +75,7 @@ static void SetValueTypeAction(MVT::ValueType VT,
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
assert(MVT::LAST_VALUETYPE <= 16 &&
assert(MVT::LAST_VALUETYPE <= 32 &&
"Too many value types for ValueTypeActions to hold!");
// Everything defaults to one.

View File

@ -192,7 +192,7 @@ def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def VRRC : RegisterClass<"PPC", f64/*FIXME*/, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
def VRRC : RegisterClass<"PPC", v4f32, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
V24, V25, V26, V27, V28, V29, V30, V31]>;

View File

@ -38,7 +38,13 @@ def f80 : ValueType<80 , 9>; // 80-bit floating point value
def f128 : ValueType<128, 10>; // 128-bit floating point value
def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
def isVoid : ValueType<0 , 12>; // Produces no value
def Vector : ValueType<0 , 13>; // Abstract vector type
def Vector : ValueType<0 , 13>; // Abstract vector value
def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target

View File

@ -34,6 +34,12 @@ const char *MVT::getValueTypeString(MVT::ValueType VT) {
case MVT::Other: return "ch";
case MVT::Flag: return "flag";
case MVT::Vector:return "vec";
case MVT::v16i8: return "v16i8";
case MVT::v8i16: return "v8i16";
case MVT::v4i32: return "v4i32";
case MVT::v2i64: return "v2i64";
case MVT::v4f32: return "v4f32";
case MVT::v2f64: return "v2f64";
}
}