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Continue Alkis's int64_t cleanup. This makes all of the immediate related

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methods take an int or unsigned value instead of int64_t.

Also, add an 'addImm' method to the MachineInstrBuilder class, because the
fact that the hardware sign or zero extends it does not/should not matter
to the code generator.  Once the old sparc backend is removed the difference
can be eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11976 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-29 05:06:49 +00:00
parent c3c106ca59
commit 6a8a9b4413
2 changed files with 22 additions and 16 deletions
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22
include/llvm/CodeGen/MachineInstr.h
View File

@ -128,7 +128,7 @@ private:
int regNum; // register number for an explicit register int regNum; // register number for an explicit register
// will be set for a value after reg allocation // will be set for a value after reg allocation
private: private:
MachineOperand(int64_t ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister) MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
: immedVal(ImmVal), : immedVal(ImmVal),
flags(0), flags(0),
opType(OpTy), opType(OpTy),
@ -228,8 +228,8 @@ public:
assert(opType == MO_MachineRegister); assert(opType == MO_MachineRegister);
return regNum; return regNum;
} }
int64_t getImmedValue() const { assert(isImmediate()); return immedVal; } int getImmedValue() const { assert(isImmediate()); return immedVal; }
void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; } void setImmedValue(int ImmVal) { assert(isImmediate()); immedVal = ImmVal; }
MachineBasicBlock *getMachineBasicBlock() const { MachineBasicBlock *getMachineBasicBlock() const {
assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
@ -522,7 +522,7 @@ public:
/// addZeroExtImmOperand - Add a zero extended constant argument to the /// addZeroExtImmOperand - Add a zero extended constant argument to the
/// machine instruction. /// machine instruction.
/// ///
void addZeroExtImmOperand(int64_t intValue) { void addZeroExtImmOperand(int intValue) {
assert(!OperandsComplete() && assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
operands.push_back( operands.push_back(
@ -532,7 +532,7 @@ public:
/// addSignExtImmOperand - Add a zero extended constant argument to the /// addSignExtImmOperand - Add a zero extended constant argument to the
/// machine instruction. /// machine instruction.
/// ///
void addSignExtImmOperand(int64_t intValue) { void addSignExtImmOperand(int intValue) {
assert(!OperandsComplete() && assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!"); "Trying to add an operand to a machine instr that is already done!");
operands.push_back( operands.push_back(
@ -600,13 +600,13 @@ public:
// Access to set the operands when building the machine instruction // Access to set the operands when building the machine instruction
// //
void SetMachineOperandVal (unsigned i, void SetMachineOperandVal(unsigned i,
MachineOperand::MachineOperandType operandType, MachineOperand::MachineOperandType operandType,
Value* V); Value* V);
void SetMachineOperandConst (unsigned i, void SetMachineOperandConst(unsigned i,
MachineOperand::MachineOperandType operandType, MachineOperand::MachineOperandType operandType,
int64_t intValue); int intValue);
void SetMachineOperandReg(unsigned i, int regNum); void SetMachineOperandReg(unsigned i, int regNum);

16
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -80,23 +80,29 @@ public:
/// addMReg - Add a machine register operand... /// addMReg - Add a machine register operand...
/// ///
const MachineInstrBuilder &addMReg( const MachineInstrBuilder &addMReg(int Reg, MachineOperand::UseType Ty
int Reg, = MachineOperand::Use) const {
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addMachineRegOperand(Reg, Ty); MI->addMachineRegOperand(Reg, Ty);
return *this; return *this;
} }
/// addImm - Add a new immediate operand.
///
const MachineInstrBuilder &addImm(int Val) const {
MI->addZeroExtImmOperand(Val);
return *this;
}
/// addSImm - Add a new sign extended immediate operand... /// addSImm - Add a new sign extended immediate operand...
/// ///
const MachineInstrBuilder &addSImm(int64_t val) const { const MachineInstrBuilder &addSImm(int val) const {
MI->addSignExtImmOperand(val); MI->addSignExtImmOperand(val);
return *this; return *this;
} }
/// addZImm - Add a new zero extended immediate operand... /// addZImm - Add a new zero extended immediate operand...
/// ///
const MachineInstrBuilder &addZImm(int64_t Val) const { const MachineInstrBuilder &addZImm(unsigned Val) const {
MI->addZeroExtImmOperand(Val); MI->addZeroExtImmOperand(Val);
return *this; return *this;
} }