From 6a9b29ec9b42e792732659e510a655449a41b661 Mon Sep 17 00:00:00 2001 From: Evgeniy Stepanov Date: Tue, 3 Sep 2013 10:04:11 +0000 Subject: [PATCH] [msan] Fix select instrumentation. Select condition shadow was being ignored resulting in false negatives. This change OR-s sign-extended condition shadow into the result shadow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189785 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Instrumentation/MemorySanitizer.cpp | 9 ++++++--- test/Instrumentation/MemorySanitizer/msan_basic.ll | 9 +++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/lib/Transforms/Instrumentation/MemorySanitizer.cpp index ae73a2e9c9e..f2cf7a76e54 100644 --- a/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -1743,9 +1743,12 @@ struct MemorySanitizerVisitor : public InstVisitor { void visitSelectInst(SelectInst& I) { IRBuilder<> IRB(&I); - setShadow(&I, IRB.CreateSelect(I.getCondition(), - getShadow(I.getTrueValue()), getShadow(I.getFalseValue()), - "_msprop")); + // a = select b, c, d + // Sa = (sext Sb) | (select b, Sc, Sd) + Value *S = IRB.CreateSelect(I.getCondition(), getShadow(I.getTrueValue()), + getShadow(I.getFalseValue())); + Value *S2 = IRB.CreateSExt(getShadow(I.getCondition()), S->getType()); + setShadow(&I, IRB.CreateOr(S, S2, "_msprop")); if (MS.TrackOrigins) { // Origins are always i32, so any vector conditions must be flattened. // FIXME: consider tracking vector origins for app vectors? diff --git a/test/Instrumentation/MemorySanitizer/msan_basic.ll b/test/Instrumentation/MemorySanitizer/msan_basic.ll index 345b070b538..466e2528dd9 100644 --- a/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -260,6 +260,8 @@ entry: ; CHECK: @Select ; CHECK: select +; CHECK-NEXT: sext i1 {{.*}} to i32 +; CHECK-NEXT: or i32 ; CHECK-NEXT: select ; CHECK: ret i32 @@ -274,6 +276,13 @@ entry: ret <8 x i16> %cond } +; CHECK: @SelectVector +; CHECK: select <8 x i1> +; CHECK-NEXT: sext <8 x i1> {{.*}} to <8 x i16> +; CHECK-NEXT: or <8 x i16> +; CHECK-NEXT: select <8 x i1> +; CHECK: ret <8 x i16> + ; CHECK-ORIGINS: @SelectVector ; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8 ; CHECK-ORIGINS: icmp ne i8