diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h
index ae97d109e33..f979bf08990 100644
--- a/include/llvm/Target/TargetSchedInfo.h
+++ b/include/llvm/Target/TargetSchedInfo.h
@@ -191,16 +191,6 @@ struct TargetSchedInfo {
   unsigned maxNumIssueTotal;
   int	longestIssueConflict;
   
-  int	branchMispredictPenalty;	// 4 for SPARC IIi
-  int	branchTargetUnknownPenalty;	// 2 for SPARC IIi
-  int   l1DCacheMissPenalty;		// 7 or 9 for SPARC IIi
-  int   l1ICacheMissPenalty;		// ? for SPARC IIi
-  
-  bool	inOrderLoads;			// true for SPARC IIi
-  bool	inOrderIssue;			// true for SPARC IIi
-  bool	inOrderExec;			// false for most architectures
-  bool	inOrderRetire;			// true for most architectures
-  
 protected:
   inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
     assert(opCode >= 0 && opCode < (int) instrRUsages.size());
diff --git a/lib/Target/SparcV9/SparcV9SchedInfo.cpp b/lib/Target/SparcV9/SparcV9SchedInfo.cpp
index 5a6104b828d..7b7da721a60 100644
--- a/lib/Target/SparcV9/SparcV9SchedInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9SchedInfo.cpp
@@ -749,16 +749,6 @@ SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
   maxNumIssueTotal = 4;
   longestIssueConflict = 0;		// computed from issuesGaps[]
   
-  branchMispredictPenalty = 4;		// 4 for SPARC IIi
-  branchTargetUnknownPenalty = 2;	// 2 for SPARC IIi
-  l1DCacheMissPenalty = 8;		// 7 or 9 for SPARC IIi
-  l1ICacheMissPenalty = 8;		// ? for SPARC IIi
-  
-  inOrderLoads = true;			// true for SPARC IIi
-  inOrderIssue = true;			// true for SPARC IIi
-  inOrderExec  = false;			// false for most architectures
-  inOrderRetire= true;			// true for most architectures
-  
   // must be called after above parameters are initialized.
   initializeResources();
 }