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The following X86 pattern is incorrect:

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def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137227 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
2011-08-10 17:45:17 +00:00
parent 1cc5e38830
commit 6ad251358e
2 changed files with 22 additions and 9 deletions
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24
test/CodeGen/X86/vec_shuffle-37.ll
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@@ -5,8 +5,8 @@
define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp {
entry:
; CHECK: movaps ({{%rdi|%rcx}}), %xmm0
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: movlps (%rax), %xmm1
; CHECK: movaps %xmm0, %xmm1
; CHECK-NEXT: movss %xmm2, %xmm1
; CHECK-NEXT: shufps $36, %xmm1, %xmm0
%0 = load <4 x i32>* undef, align 16
%1 = load <4 x i32>* %a0, align 16
@@ -23,3 +23,23 @@ entry:
store <2 x double> %vecinit94, <2 x double>* undef
ret void
}
define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline {
entry:
; CHECK: movaps 32({{%rdi|%rcx}}), %xmm0
; CHECK-NEXT: movaps 48({{%rdi|%rcx}}), %xmm1
; CHECK-NEXT: movss %xmm1, %xmm0
; CHECK-NEXT: movq %xmm0, ({{%rsi|%rdx}})
%0 = bitcast <8 x i32>* %source to <4 x i32>*
%arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3
%tmp2 = load <4 x i32>* %arrayidx, align 16
%tmp3 = extractelement <4 x i32> %tmp2, i32 0
%tmp5 = insertelement <2 x i32> <i32 undef, i32 0>, i32 %tmp3, i32 0
%arrayidx7 = getelementptr inbounds <8 x i32>* %source, i64 1
%1 = bitcast <8 x i32>* %arrayidx7 to <4 x i32>*
%tmp8 = load <4 x i32>* %1, align 16
%tmp9 = extractelement <4 x i32> %tmp8, i32 1
%tmp11 = insertelement <2 x i32> %tmp5, i32 %tmp9, i32 1
store <2 x i32> %tmp11, <2 x i32>* %dest, align 8
ret void
}