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https://github.com/c64scene-ar/llvm-6502.git
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Do the same for float->int that we did for int->float earlier.
Also check IsPointerType() in addition to IsIntegral() in several places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1227 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
5b6082eccf
commit
6ad7c553fd
@ -324,9 +324,9 @@ ChooseAddInstructionByType(const Type* resultType)
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MachineOpCode opCode = INVALID_OPCODE;
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if (resultType->isIntegral() ||
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isa<PointerType>(resultType) ||
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isa<MethodType>(resultType) ||
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resultType->isPointerType() ||
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resultType->isLabelType() ||
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isa<MethodType>(resultType) ||
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resultType == Type::BoolTy)
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{
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opCode = ADD;
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@ -519,8 +519,8 @@ CreateMulConstInstruction(TargetMachine &target,
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const InstructionNode* instrNode,
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MachineInstr*& getMinstr2)
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{
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MachineInstr* minstr = NULL;
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getMinstr2 = NULL;
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MachineInstr* minstr = NULL; // return NULL if we cannot exploit constant
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getMinstr2 = NULL; // to create a cheaper instruction
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bool needNeg = false;
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Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
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@ -580,32 +580,20 @@ CreateMulConstInstruction(TargetMachine &target,
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if (resultType == Type::FloatTy ||
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resultType == Type::DoubleTy)
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{
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bool isValidConst;
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double dval = ((ConstPoolFP*) constOp)->getValue();
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if (isValidConst)
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if (fabs(dval) == 1)
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{
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if (dval == 0)
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{
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minstr = new MachineInstr((resultType == Type::FloatTy)
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? FITOS : FITOD);
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minstr->SetMachineOperand(0,
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target.getRegInfo().getZeroRegNum());
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}
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else if (fabs(dval) == 1)
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{
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bool needNeg = (dval < 0);
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MachineOpCode opCode = needNeg
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? (resultType == Type::FloatTy? FNEGS : FNEGD)
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: (resultType == Type::FloatTy? FMOVS : FMOVD);
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minstr = new MachineInstr(opCode);
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minstr->SetMachineOperand(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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}
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}
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bool needNeg = (dval < 0);
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MachineOpCode opCode = needNeg
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? (resultType == Type::FloatTy? FNEGS : FNEGD)
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: (resultType == Type::FloatTy? FMOVS : FMOVD);
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minstr = new MachineInstr(opCode);
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minstr->SetMachineOperand(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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}
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}
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}
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@ -705,10 +693,8 @@ CreateDivConstInstruction(TargetMachine &target,
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if (resultType == Type::FloatTy ||
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resultType == Type::DoubleTy)
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{
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bool isValidConst;
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double dval = ((ConstPoolFP*) constOp)->getValue();
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if (isValidConst && fabs(dval) == 1)
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if (fabs(dval) == 1)
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{
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bool needNeg = (dval < 0);
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@ -1139,8 +1125,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{
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int numInstr = 1; // initialize for common case
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bool checkCast = false; // initialize here to use fall-through
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Value *leftVal, *rightVal;
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const Type* opType;
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int nextRule;
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int forwardOperandNum = -1;
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int64_t s0=0, s8=8; // variables holding constants to avoid
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@ -1365,42 +1349,94 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 322: // reg: ToBoolTy(bool):
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case 22: // reg: ToBoolTy(reg):
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opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType == Type::BoolTy);
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{
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const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() || opType->isPointerType()
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|| opType == Type::BoolTy);
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numInstr = 0;
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forwardOperandNum = 0;
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break;
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}
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case 23: // reg: ToUByteTy(reg)
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case 25: // reg: ToUShortTy(reg)
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case 27: // reg: ToUIntTy(reg)
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case 29: // reg: ToULongTy(reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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{
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const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral() ||
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opType->isPointerType() ||
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opType == Type::BoolTy && "Cast is illegal for other types");
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numInstr = 0;
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forwardOperandNum = 0;
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break;
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}
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case 24: // reg: ToSByteTy(reg)
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case 26: // reg: ToShortTy(reg)
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case 28: // reg: ToIntTy(reg)
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case 30: // reg: ToLongTy(reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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if (opType->isIntegral() || opType == Type::BoolTy)
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{
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const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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if (opType->isIntegral()
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|| opType->isPointerType()
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|| opType == Type::BoolTy)
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{
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numInstr = 0;
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forwardOperandNum = 0;
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}
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else
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{
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mvec[0] = new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,
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opType));
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Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
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// If the source operand is an FP type, the int result must be
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// copied from float to int register via memory!
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Instruction *dest = subtreeRoot->getInstruction();
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Value* leftVal = subtreeRoot->leftChild()->getValue();
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Value* destForCast;
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vector<MachineInstr*> minstrVec;
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if (opType == Type::FloatTy || opType == Type::DoubleTy)
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{
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// Create a temporary to represent the INT register
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// into which the FP value will be copied via memory.
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// The type of this temporary will determine the FP
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// register used: single-prec for a 32-bit int or smaller,
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// double-prec for a 64-bit int.
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//
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const Type* destTypeToUse =
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(dest->getType() == Type::LongTy)? Type::DoubleTy
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: Type::FloatTy;
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destForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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destTypeToUse, leftVal, NULL);
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dest->getMachineInstrVec().addTempValue(destForCast);
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vector<TmpInstruction*> tempVec;
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target.getInstrInfo().CreateCodeToCopyFloatToInt(
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dest->getParent()->getParent(),
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(TmpInstruction*) destForCast, dest,
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minstrVec, tempVec, target);
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for (unsigned i=0; i < tempVec.size(); ++i)
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dest->getMachineInstrVec().addTempValue(tempVec[i]);
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}
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else
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destForCast = leftVal;
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MachineOpCode opCode=ChooseConvertToIntInstr(subtreeRoot, opType);
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assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
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mvec[0] = new MachineInstr(opCode);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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leftVal);
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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destForCast);
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assert(numInstr == 1 && "Should be initialized to 1 at the top");
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for (unsigned i=0; i < minstrVec.size(); ++i)
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mvec[numInstr++] = minstrVec[i];
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}
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break;
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}
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case 31: // reg: ToFloatTy(reg):
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case 32: // reg: ToDoubleTy(reg):
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case 232: // reg: ToDoubleTy(Constant):
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@ -1419,8 +1455,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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else
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{
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leftVal = subtreeRoot->leftChild()->getValue();
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opType = leftVal->getType();
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Value* leftVal = subtreeRoot->leftChild()->getValue();
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const Type* opType = leftVal->getType();
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MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
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if (opCode == INVALID_OPCODE) // no conversion needed
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{
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@ -1438,8 +1474,16 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{
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// Create a temporary to represent the FP register
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// into which the integer will be copied via memory.
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// The type of this temporary will determine the FP
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// register used: single-prec for a 32-bit int or smaller,
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// double-prec for a 64-bit int.
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//
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const Type* srcTypeToUse =
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(leftVal->getType() == Type::LongTy)? Type::DoubleTy
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: Type::FloatTy;
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srcForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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dest, NULL);
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srcTypeToUse, dest, NULL);
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dest->getMachineInstrVec().addTempValue(srcForCast);
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vector<MachineInstr*> minstrVec;
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@ -1627,8 +1671,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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//
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// Otherwise this is just the same as case 42, so just fall through.
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//
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if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() &&
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subtreeRoot->parent() != NULL)
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if ((subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
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subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
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&& subtreeRoot->parent() != NULL)
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{
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InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
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assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
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@ -1684,7 +1729,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// condition code. Think of this as casting the bool result to
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// a FP condition code register.
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//
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leftVal = subtreeRoot->leftChild()->getValue();
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Value* leftVal = subtreeRoot->leftChild()->getValue();
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bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
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leftVal->getType() == Type::DoubleTy);
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@ -1938,16 +1983,17 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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case 62: // reg: Shl(reg, reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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{ const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral()
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|| opType == Type::BoolTy
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|| opType->isPointerType()&& "Shl unsupported for other types");
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mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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}
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case 63: // reg: Shr(reg, reg)
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opType = subtreeRoot->leftChild()->getValue()->getType();
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{ const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
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assert(opType->isIntegral()
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|| opType == Type::BoolTy
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|| opType->isPointerType() &&"Shr unsupported for other types");
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@ -1956,7 +2002,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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: ((opType == Type::LongTy)? SRLX : SRL)));
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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}
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case 64: // reg: Phi(reg,reg)
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{ // This instruction has variable #operands, so resultPos is 0.
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Instruction* phi = subtreeRoot->getInstruction();
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@ -1968,6 +2015,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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phi->getOperand(i));
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break;
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}
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case 71: // reg: VReg
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case 72: // reg: Constant
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numInstr = 0; // don't forward the value
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