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Teach the x86 backend about the register constraints of its addressing mode.

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Patch by Evan Cheng


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-11-19 07:01:30 +00:00
parent be7a2ff2dd
commit 6adaf79ad7
1 changed files with 2 additions and 1 deletions
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3
lib/Target/X86/X86InstrInfo.td
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@ -17,8 +17,9 @@
//
class X86MemOperand<ValueType Ty> : Operand<Ty> {
let NumMIOperands = 4;
let PrintMethod = "printMemoryOperand";
let NumMIOperands = 4;
let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
}
def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";