diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 4b419ad9e28..9e28f2cf97e 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1473,9 +1473,6 @@ bool MipsAsmParser::searchSymbolAlias( MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { - if (isMips64()) - return MatchOperand_NoMatch; - // If the first token is not '$' we have error. if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index c12cc9091cb..51a84a9611e 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -75,6 +75,8 @@ def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith, immSExt16, add>, ADDI_FM<0x19>, IsAsCheapAsAMove; + +let isCodeGenOnly = 1 in { def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64RegsOpnd>, SLTI_FM<0xa>; def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64RegsOpnd>, @@ -89,6 +91,7 @@ def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16, xor>, ADDI_FM<0xe>; def LUi64 : LoadUpper<"lui", CPU64RegsOpnd, uimm16_64>, LUI_FM; +} /// Arithmetic Instructions (3-Operand, R-Type) def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; @@ -119,36 +122,39 @@ def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; -} + // Rotate Instructions -let Predicates = [HasMips64r2, HasStdEnc], - DecoderNamespace = "Mips64" in { +let Predicates = [HasMips64r2, HasStdEnc] in { def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, SRA_FM<0x3a, 1>; def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, SRLV_FM<0x16, 1>; } -let DecoderNamespace = "Mips64" in { /// Load and Store Instructions /// aligned +let isCodeGenOnly = 1 in { defm LB64 : LoadM<"lb", CPU64RegsOpnd, sextloadi8, IILoad>, LW_FM<0x20>; defm LBu64 : LoadM<"lbu", CPU64RegsOpnd, zextloadi8, IILoad>, LW_FM<0x24>; defm LH64 : LoadM<"lh", CPU64RegsOpnd, sextloadi16, IILoad>, LW_FM<0x21>; defm LHu64 : LoadM<"lhu", CPU64RegsOpnd, zextloadi16, IILoad>, LW_FM<0x25>; defm LW64 : LoadM<"lw", CPU64RegsOpnd, sextloadi32, IILoad>, LW_FM<0x23>; -defm LWu64 : LoadM<"lwu", CPU64RegsOpnd, zextloadi32, IILoad>, LW_FM<0x27>; defm SB64 : StoreM<"sb", CPU64RegsOpnd, truncstorei8, IIStore>, LW_FM<0x28>; defm SH64 : StoreM<"sh", CPU64RegsOpnd, truncstorei16, IIStore>, LW_FM<0x29>; defm SW64 : StoreM<"sw", CPU64RegsOpnd, truncstorei32, IIStore>, LW_FM<0x2b>; +} + +defm LWu : LoadM<"lwu", CPU64RegsOpnd, zextloadi32, IILoad>, LW_FM<0x27>; defm LD : LoadM<"ld", CPU64RegsOpnd, load, IILoad>, LW_FM<0x37>; defm SD : StoreM<"sd", CPU64RegsOpnd, store, IIStore>, LW_FM<0x3f>; /// load/store left/right +let isCodeGenOnly = 1 in { defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64RegsOpnd>, LW_FM<0x22>; defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64RegsOpnd>, LW_FM<0x26>; defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64RegsOpnd>, LW_FM<0x2a>; defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64RegsOpnd>, LW_FM<0x2e>; +} defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64RegsOpnd>, LW_FM<0x1a>; defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64RegsOpnd>, LW_FM<0x1b>; @@ -167,6 +173,7 @@ let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { } /// Jump and Branch Instructions +let isCodeGenOnly = 1 in { def JR64 : IndirectBranch, MTLO_FM<8>; def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>; def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>; @@ -174,16 +181,11 @@ def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>; def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>; def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>; def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>; -} - -let DecoderNamespace = "Mips64", isCodeGenOnly = 1 in { def JALR64 : JumpLinkReg<"jalr", CPU64RegsOpnd>, JALR_FM; def JALR64Pseudo : JumpLinkRegPseudo; +def TAILCALL64_R : JumpFR, MTLO_FM<8>, IsTailCall; } -def TAILCALL64_R : JumpFR, MTLO_FM<8>, IsTailCall; - -let DecoderNamespace = "Mips64" in { /// Multiply and Divide Instructions. def DMULT : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1c>; @@ -200,6 +202,7 @@ def PseudoDSDIV : MultDivPseudo; +let isCodeGenOnly = 1 in { def MTHI64 : MoveToLOHI<"mthi", CPU64RegsOpnd, [HI64]>, MTLO_FM<0x11>; def MTLO64 : MoveToLOHI<"mtlo", CPU64RegsOpnd, [LO64]>, MTLO_FM<0x13>; def MFHI64 : MoveFromLOHI<"mfhi", CPU64RegsOpnd, [HI64]>, MFLO_FM<0x10>; @@ -208,6 +211,7 @@ def MFLO64 : MoveFromLOHI<"mflo", CPU64RegsOpnd, [LO64]>, MFLO_FM<0x12>; /// Sign Ext In Register Instructions. def SEB64 : SignExtInReg<"seb", i8, CPU64RegsOpnd>, SEB_FM<0x10, 0x20>; def SEH64 : SignExtInReg<"seh", i16, CPU64RegsOpnd>, SEB_FM<0x18, 0x20>; +} /// Count Leading def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; @@ -219,8 +223,7 @@ def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64RegsOpnd, mem_ea_64>, LW_FM<0x19>; -} -let DecoderNamespace = "Mips64" in { +let isCodeGenOnly = 1 in def RDHWR64 : ReadHardware, RDHWR_FM; def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index 74593a68eeb..766cd267509 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -105,49 +105,41 @@ multiclass MovnPats, ADD_FM<0, 0xa>; -let Predicates = [HasStdEnc], - DecoderNamespace = "Mips64" in { + +let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { def MOVZ_I_I64 : CMov_I_I_FT<"movz", CPURegsOpnd, CPU64RegsOpnd, NoItinerary>, ADD_FM<0, 0xa>; def MOVZ_I64_I : CMov_I_I_FT<"movz", CPU64RegsOpnd, CPURegsOpnd, - NoItinerary>, ADD_FM<0, 0xa> { - let isCodeGenOnly = 1; - } + NoItinerary>, ADD_FM<0, 0xa>; def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64RegsOpnd, CPU64RegsOpnd, - NoItinerary>, ADD_FM<0, 0xa> { - let isCodeGenOnly = 1; - } + NoItinerary>, ADD_FM<0, 0xa>; } def MOVN_I_I : CMov_I_I_FT<"movn", CPURegsOpnd, CPURegsOpnd, NoItinerary>, ADD_FM<0, 0xb>; -let Predicates = [HasStdEnc], - DecoderNamespace = "Mips64" in { + +let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { def MOVN_I_I64 : CMov_I_I_FT<"movn", CPURegsOpnd, CPU64RegsOpnd, NoItinerary>, ADD_FM<0, 0xb>; def MOVN_I64_I : CMov_I_I_FT<"movn", CPU64RegsOpnd, CPURegsOpnd, - NoItinerary>, ADD_FM<0, 0xb> { - let isCodeGenOnly = 1; - } + NoItinerary>, ADD_FM<0, 0xb>; def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64RegsOpnd, CPU64RegsOpnd, - NoItinerary>, ADD_FM<0, 0xb> { - let isCodeGenOnly = 1; - } + NoItinerary>, ADD_FM<0, 0xb>; } def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegsOpnd, FGR32RegsOpnd, IIFmove>, CMov_I_F_FM<18, 16>; + +let isCodeGenOnly = 1 in def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64RegsOpnd, FGR32RegsOpnd, IIFmove>, - CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; -} + CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>; def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegsOpnd, FGR32RegsOpnd, IIFmove>, CMov_I_F_FM<19, 16>; + +let isCodeGenOnly = 1 in def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64RegsOpnd, FGR32RegsOpnd, IIFmove>, - CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; -} + CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>; let Predicates = [NotFP64bit, HasStdEnc] in { def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegsOpnd, AFGR64RegsOpnd, IIFmove>, @@ -155,35 +147,31 @@ let Predicates = [NotFP64bit, HasStdEnc] in { def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegsOpnd, AFGR64RegsOpnd, IIFmove>, CMov_I_F_FM<19, 17>; } -let Predicates = [IsFP64bit, HasStdEnc], - DecoderNamespace = "Mips64" in { + +let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegsOpnd, FGR64RegsOpnd, IIFmove>, CMov_I_F_FM<18, 17>; def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64RegsOpnd, FGR64RegsOpnd, - IIFmove>, CMov_I_F_FM<18, 17> { - let isCodeGenOnly = 1; - } + IIFmove>, CMov_I_F_FM<18, 17>; def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegsOpnd, FGR64RegsOpnd, IIFmove>, CMov_I_F_FM<19, 17>; def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64RegsOpnd, FGR64RegsOpnd, - IIFmove>, CMov_I_F_FM<19, 17> { - let isCodeGenOnly = 1; - } + IIFmove>, CMov_I_F_FM<19, 17>; } def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIArith, MipsCMovFP_T>, CMov_F_I_FM<1>; + +let isCodeGenOnly = 1 in def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIArith, MipsCMovFP_T>, - CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; -} + CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>; def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIArith, MipsCMovFP_F>, CMov_F_I_FM<0>; + +let isCodeGenOnly = 1 in def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIArith, MipsCMovFP_F>, - CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; -} + CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>; def MOVT_S : CMov_F_F_FT<"movt.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_T>, CMov_F_F_FM<16, 1>; @@ -196,8 +184,7 @@ let Predicates = [NotFP64bit, HasStdEnc] in { def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_F>, CMov_F_F_FM<17, 0>; } -let Predicates = [IsFP64bit, HasStdEnc], - DecoderNamespace = "Mips64" in { +let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_F>,