mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 00:32:55 +00:00
modified machine code printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@595 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
427a527311
commit
6b0a8b5b1a
@ -1,6 +1,14 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(const Method *const M,
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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@ -21,10 +29,10 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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@ -64,11 +72,12 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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@ -123,7 +132,10 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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@ -190,6 +202,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a method.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs()
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{
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// get the InSet of root BB
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@ -213,6 +228,11 @@ void PhyRegAlloc::addInterferencesForArgs()
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::updateMachineCode()
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{
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@ -244,6 +264,7 @@ void PhyRegAlloc::updateMachineCode()
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// delete this condition checking later (must assert if Val is null)
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if( !Val ) {
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cout << "Error: NULL Value found in instr." << endl;
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Op.setRegForValue( 10000 ); // an invalid value is set
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continue;
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}
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assert( Val && "Value is NULL");
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@ -277,6 +298,148 @@ void PhyRegAlloc::updateMachineCode()
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//----------------------------------------------------------------------------
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// This method prints the code with registers after register allocation is
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// complete.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::printMachineCode()
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{
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cout << endl << ";************** Method ";
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cout << Meth->getName() << " *****************" << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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cout << endl ; printLabel( *BBI); cout << ": ";
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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cout << endl << "\t";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister ||
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Op.getOperandType() == MachineOperand::MO_MachineRegister ) {
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const int RegNum = Op.getAllocatedRegNum();
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// ****this code is temporary till NULL Values are fixed
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if( RegNum == 10000) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum);
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}
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else if( Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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if( !Val ) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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if( (Val->getValueType() == Value::BasicBlockVal))
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{ cout << "\t"; printLabel( Op.getVRegValue () ); }
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else { cout << "\t"; printValue( Val ); }
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}
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else
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cout << "\t" << Op; // use dump field
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}
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}
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cout << endl;
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}
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cout << endl;
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}
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void PhyRegAlloc::printLabel(const Value *const Val)
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{
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if( Val->hasName() )
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cout << Val->getName();
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else
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cout << "Label" << Val;
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}
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void PhyRegAlloc::allocateRegisters()
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{
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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LRI.coalesceLRs(); // coalesce all live ranges
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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MRI.colorArgs(Meth, LRI); // color method args
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// color call args of call instrns
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MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
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// color all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->colorAllRegs();
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updateMachineCode();
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PrintMachineInstructions(Meth);
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printMachineCode(); // only for DEBUGGING
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}
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#if 0
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void PhyRegAlloc::printMachineCode()
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{
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@ -384,60 +547,4 @@ void PhyRegAlloc::printLabel(const Value *const Val)
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cout << "Label" << Val;
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}
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void PhyRegAlloc::allocateRegisters()
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{
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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LRI.coalesceLRs(); // coalesce all live ranges
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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MRI.colorArgs(Meth, LRI); // color method args
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// color call args of call instrns
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MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
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// color all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->colorAllRegs();
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//updateMachineCode();
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PrintMachineInstructions(Meth);
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printMachineCode(); // only for DEBUGGING
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}
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#endif
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@ -1,6 +1,14 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(const Method *const M,
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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@ -21,10 +29,10 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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@ -64,11 +72,12 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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@ -123,7 +132,10 @@ void PhyRegAlloc::addInterference(const Value *const Def,
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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@ -190,6 +202,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a method.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs()
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{
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// get the InSet of root BB
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@ -213,6 +228,11 @@ void PhyRegAlloc::addInterferencesForArgs()
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::updateMachineCode()
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{
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@ -244,6 +264,7 @@ void PhyRegAlloc::updateMachineCode()
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// delete this condition checking later (must assert if Val is null)
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if( !Val ) {
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cout << "Error: NULL Value found in instr." << endl;
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Op.setRegForValue( 10000 ); // an invalid value is set
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continue;
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}
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assert( Val && "Value is NULL");
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@ -277,6 +298,148 @@ void PhyRegAlloc::updateMachineCode()
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//----------------------------------------------------------------------------
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// This method prints the code with registers after register allocation is
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// complete.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::printMachineCode()
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{
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cout << endl << ";************** Method ";
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cout << Meth->getName() << " *****************" << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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cout << endl ; printLabel( *BBI); cout << ": ";
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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cout << endl << "\t";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister ||
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Op.getOperandType() == MachineOperand::MO_MachineRegister ) {
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const int RegNum = Op.getAllocatedRegNum();
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// ****this code is temporary till NULL Values are fixed
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if( RegNum == 10000) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum);
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}
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else if( Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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if( !Val ) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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if( (Val->getValueType() == Value::BasicBlockVal))
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{ cout << "\t"; printLabel( Op.getVRegValue () ); }
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else { cout << "\t"; printValue( Val ); }
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}
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else
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cout << "\t" << Op; // use dump field
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}
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}
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cout << endl;
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}
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cout << endl;
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}
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void PhyRegAlloc::printLabel(const Value *const Val)
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{
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if( Val->hasName() )
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cout << Val->getName();
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else
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cout << "Label" << Val;
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}
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void PhyRegAlloc::allocateRegisters()
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{
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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LRI.coalesceLRs(); // coalesce all live ranges
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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MRI.colorArgs(Meth, LRI); // color method args
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// color call args of call instrns
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MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
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// color all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->colorAllRegs();
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updateMachineCode();
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PrintMachineInstructions(Meth);
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printMachineCode(); // only for DEBUGGING
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}
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#if 0
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void PhyRegAlloc::printMachineCode()
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{
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@ -384,60 +547,4 @@ void PhyRegAlloc::printLabel(const Value *const Val)
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cout << "Label" << Val;
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}
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void PhyRegAlloc::allocateRegisters()
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{
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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LRI.printLiveRanges();
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|
||||
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
||||
|
||||
buildInterferenceGraphs(); // build IGs in all reg classes
|
||||
|
||||
|
||||
if( DEBUG_RA) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
}
|
||||
|
||||
LRI.coalesceLRs(); // coalesce all live ranges
|
||||
|
||||
if( DEBUG_RA) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
}
|
||||
|
||||
MRI.colorArgs(Meth, LRI); // color method args
|
||||
// color call args of call instrns
|
||||
MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
|
||||
|
||||
// color all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->colorAllRegs();
|
||||
|
||||
//updateMachineCode();
|
||||
PrintMachineInstructions(Meth);
|
||||
printMachineCode(); // only for DEBUGGING
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user