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[x86] Add tests for blends-with-zero on 4-element vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228122 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -657,6 +657,98 @@ define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0z23(<4 x float> %a) {
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; SSE-LABEL: shuffle_v4f32_0z23:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z23:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,3]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_01z3(<4 x float> %a) {
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; SSE-LABEL: shuffle_v4f32_01z3:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_01z3:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_012z(<4 x float> %a) {
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; SSE2-LABEL: shuffle_v4f32_012z:
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; SSE2: # BB#0:
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; SSE2-NEXT: xorps %xmm1, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: shuffle_v4f32_012z:
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; SSE3: # BB#0:
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; SSE3-NEXT: xorps %xmm1, %xmm1
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; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v4f32_012z:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: xorps %xmm1, %xmm1
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v4f32_012z:
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; SSE41: # BB#0:
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; SSE41-NEXT: xorps %xmm1, %xmm1
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_012z:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0zz3(<4 x float> %a) {
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; SSE-LABEL: shuffle_v4f32_0zz3:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0zz3:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_4zzz(<4 x i32> %a) {
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; SSE2-LABEL: shuffle_v4i32_4zzz:
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; SSE2: # BB#0:
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@ -1090,6 +1182,104 @@ define <4 x i32> @shuffle_v4i32_01zu(<4 x i32> %a) {
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_0z23(<4 x i32> %a) {
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; SSE-LABEL: shuffle_v4i32_0z23:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4i32_0z23:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[2,3]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_01z3(<4 x i32> %a) {
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; SSE-LABEL: shuffle_v4i32_01z3:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4i32_01z3:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_012z(<4 x i32> %a) {
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; SSE2-LABEL: shuffle_v4i32_012z:
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; SSE2: # BB#0:
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; SSE2-NEXT: xorps %xmm1, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: shuffle_v4i32_012z:
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; SSE3: # BB#0:
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; SSE3-NEXT: xorps %xmm1, %xmm1
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; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: shuffle_v4i32_012z:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: xorps %xmm1, %xmm1
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm0[2,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: shuffle_v4i32_012z:
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; SSE41: # BB#0:
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; SSE41-NEXT: pxor %xmm1, %xmm1
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: shuffle_v4i32_012z:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v4i32_012z:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_0zz3(<4 x i32> %a) {
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; SSE-LABEL: shuffle_v4i32_0zz3:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4i32_0zz3:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,0]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @insert_reg_and_zero_v4i32(i32 %a) {
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; SSE-LABEL: insert_reg_and_zero_v4i32:
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; SSE: # BB#0:
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