6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-18 12:29:21 +00:00
Code Issues Projects Releases Wiki Activity

revert the previous patch, didn't mean to check it in yet

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-08 04:39:05 +00:00
parent 5874f82564
commit 6b24af87e6
1 changed files with 2 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1795,33 +1795,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
break;
case TargetLowering::Legal: break;
case TargetLowering::Expand:
// If this target supports fabs/fneg natively, do this efficiently.
if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
// Get the sign bit of the RHS.
MVT::ValueType IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
// Get the absolute value of the result.
SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
break;
}
// Otherwise, do bitwise ops!
// copysign -> copysignf/copysign libcall.
// Floating point mod -> fmod libcall.
const char *FnName;
if (Node->getValueType(0) == MVT::f32) {
FnName = "copysignf";