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Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"
This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238821 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1470,7 +1470,8 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr *MI = &*MBBI;
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM::LDRD || Opcode == ARM::STRD) {
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if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
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Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
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const MachineOperand &BaseOp = MI->getOperand(2);
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unsigned BaseReg = BaseOp.getReg();
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unsigned EvenReg = MI->getOperand(0).getReg();
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@@ -1948,11 +1949,10 @@ static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0,
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bool
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ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
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DebugLoc &dl, unsigned &NewOpc,
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unsigned &FirstReg,
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unsigned &SecondReg,
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unsigned &BaseReg, int &Offset,
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unsigned &PredReg,
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DebugLoc &dl,
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unsigned &NewOpc, unsigned &EvenReg,
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unsigned &OddReg, unsigned &BaseReg,
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int &Offset, unsigned &PredReg,
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ARMCC::CondCodes &Pred,
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bool &isT2) {
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// Make sure we're allowed to generate LDRD/STRD.
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@@ -2011,9 +2011,9 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
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return false;
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Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
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}
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FirstReg = Op0->getOperand(0).getReg();
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SecondReg = Op1->getOperand(0).getReg();
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if (FirstReg == SecondReg)
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EvenReg = Op0->getOperand(0).getReg();
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OddReg = Op1->getOperand(0).getReg();
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if (EvenReg == OddReg)
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return false;
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BaseReg = Op0->getOperand(1).getReg();
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Pred = getInstrPredicate(Op0, PredReg);
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@@ -2109,7 +2109,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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// to try to allocate a pair of registers that can form register pairs.
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MachineInstr *Op0 = Ops.back();
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MachineInstr *Op1 = Ops[Ops.size()-2];
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unsigned FirstReg = 0, SecondReg = 0;
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unsigned EvenReg = 0, OddReg = 0;
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unsigned BaseReg = 0, PredReg = 0;
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ARMCC::CondCodes Pred = ARMCC::AL;
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bool isT2 = false;
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@@ -2117,21 +2117,21 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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int Offset = 0;
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DebugLoc dl;
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if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
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FirstReg, SecondReg, BaseReg,
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EvenReg, OddReg, BaseReg,
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Offset, PredReg, Pred, isT2)) {
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Ops.pop_back();
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Ops.pop_back();
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const MCInstrDesc &MCID = TII->get(NewOpc);
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const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
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MRI->constrainRegClass(FirstReg, TRC);
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MRI->constrainRegClass(SecondReg, TRC);
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MRI->constrainRegClass(EvenReg, TRC);
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MRI->constrainRegClass(OddReg, TRC);
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// Form the pair instruction.
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if (isLd) {
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MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
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.addReg(FirstReg, RegState::Define)
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.addReg(SecondReg, RegState::Define)
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.addReg(EvenReg, RegState::Define)
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.addReg(OddReg, RegState::Define)
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.addReg(BaseReg);
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// FIXME: We're converting from LDRi12 to an insn that still
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// uses addrmode2, so we need an explicit offset reg. It should
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@@ -2144,8 +2144,8 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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++NumLDRDFormed;
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} else {
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MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
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.addReg(FirstReg)
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.addReg(SecondReg)
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.addReg(EvenReg)
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.addReg(OddReg)
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.addReg(BaseReg);
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// FIXME: We're converting from LDRi12 to an insn that still
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// uses addrmode2, so we need an explicit offset reg. It should
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@@ -2160,11 +2160,9 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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MBB->erase(Op0);
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MBB->erase(Op1);
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if (!isT2) {
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// Add register allocation hints to form register pairs.
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MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
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MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg);
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}
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// Add register allocation hints to form register pairs.
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MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
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MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
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} else {
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for (unsigned i = 0; i != NumMove; ++i) {
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MachineInstr *Op = Ops.back();
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