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Fix, correctly this time, the computation of the return value
Fix a spello Tighten up the assertion checking No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11036 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -73,8 +73,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(std::cerr << "Machine Function\n");
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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bool MadeChange = false;
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bool MadeChange = false;
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@ -90,19 +90,20 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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continue;
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continue;
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++numTwoAddressInstrs;
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++numTwoAddressInstrs;
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MadeChange = true;
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DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
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DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
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assert(mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getAllocatedRegNum() &&
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mi->getOperand(1).isUse() &&
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"two address instruction invalid");
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// we have nothing to do if the two operands are the same
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// we have nothing to do if the two operands are the same
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if (mi->getOperand(0).getAllocatedRegNum() ==
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if (mi->getOperand(0).getAllocatedRegNum() ==
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mi->getOperand(1).getAllocatedRegNum())
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mi->getOperand(1).getAllocatedRegNum())
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continue;
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continue;
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assert(mi->getOperand(1).isRegister() &&
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MadeChange = true;
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mi->getOperand(1).getAllocatedRegNum() &&
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mi->getOperand(1).isUse() &&
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"two address instruction invalid");
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// rewrite:
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// rewrite:
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// a = b op c
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// a = b op c
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@ -112,28 +113,28 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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unsigned regA = mi->getOperand(0).getAllocatedRegNum();
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unsigned regA = mi->getOperand(0).getAllocatedRegNum();
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unsigned regB = mi->getOperand(1).getAllocatedRegNum();
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unsigned regB = mi->getOperand(1).getAllocatedRegNum();
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assert(regA >= MRegisterInfo::FirstVirtualRegister &&
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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regB >= MRegisterInfo::FirstVirtualRegister &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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"cannot update physical register live information");
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// first make sure we do not have a use of a in the
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// first make sure we do not have a use of a in the
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// instruction (a = b + a for example) because our
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// instruction (a = b + a for example) because our
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// transofrmation will not work. This should never occur
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// transformation will not work. This should never occur
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// because of SSA.
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// because we are in SSA form.
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for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getAllocatedRegNum() != (int)regA);
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mi->getOperand(i).getAllocatedRegNum() != (int)regA);
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}
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const TargetRegisterClass* rc =
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const TargetRegisterClass* rc =MF.getSSARegMap()->getRegClass(regA);
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MF.getSSARegMap()->getRegClass(regA);
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unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
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numInstrsAdded += MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
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numInstrsAdded += Added;
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MachineInstr* prevMi = *(mii - 1);
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MachineInstr* prevMi = *(mii - 1);
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DEBUG(std::cerr << "\t\tadded instruction: ";
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DEBUG(std::cerr << "\t\tadded instruction: ";
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prevMi->print(std::cerr, TM));
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prevMi->print(std::cerr, TM));
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// update live variables for regA
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// update live variables for regA
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assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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varInfo.DefInst = prevMi;
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