6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-28 21:34:23 +00:00
Code Issues Projects Releases Wiki Activity

Fix a typo.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-09-18 23:28:33 +00:00
parent 47a7e2681e
commit 6b5578f052
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2331,14 +2331,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
break;
case TargetLowering::Expand:
unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SREM;
unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
if (MVT::isInteger(Node->getValueType(0))) {
if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
TargetLowering::Legal) {
// X % Y -> X-X/Y*Y
MVT::ValueType VT = Node->getValueType(0);
unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
} else {