From 6b61cd185eeb90bec93f042535594132ae1f0f41 Mon Sep 17 00:00:00 2001 From: Tilmann Scheller Date: Fri, 3 Jul 2009 06:44:53 +0000 Subject: [PATCH] Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call. With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack. The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 3 ++- include/llvm/CodeGen/SelectionDAGNodes.h | 11 +++++++++-- include/llvm/Target/TargetLowering.h | 6 +++--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 ++-- lib/CodeGen/SelectionDAG/LegalizeTypes.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 11 ++++++----- lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 10 +++++----- lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/Alpha/AlphaISelLowering.cpp | 3 ++- lib/Target/Alpha/AlphaISelLowering.h | 6 +++--- lib/Target/CellSPU/SPUISelLowering.cpp | 2 +- lib/Target/IA64/IA64ISelLowering.cpp | 3 ++- lib/Target/IA64/IA64ISelLowering.h | 2 +- lib/Target/PIC16/PIC16ISelLowering.cpp | 5 +++-- lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 2 +- 16 files changed, 43 insertions(+), 31 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 3ba5f301933..8abd78dd2ab 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -536,7 +536,8 @@ public: /// SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool isInreg, SDVTList VTs, - const SDValue *Operands, unsigned NumOperands); + const SDValue *Operands, unsigned NumOperands, + unsigned NumFixedArgs); /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index adf04782d09..975253751c8 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -2257,6 +2257,7 @@ class CallSDNode : public SDNode { unsigned CallingConv; bool IsVarArg; bool IsTailCall; + unsigned NumFixedArgs; // We might eventually want a full-blown Attributes for the result; that // will expand the size of the representation. At the moment we only // need Inreg. @@ -2264,10 +2265,10 @@ class CallSDNode : public SDNode { friend class SelectionDAG; CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall, bool isinreg, SDVTList VTs, const SDValue *Operands, - unsigned numOperands) + unsigned numOperands, unsigned numFixedArgs) : SDNode(ISD::CALL, dl, VTs, Operands, numOperands), CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall), - Inreg(isinreg) {} + NumFixedArgs(numFixedArgs), Inreg(isinreg) {} public: unsigned getCallingConv() const { return CallingConv; } unsigned isVarArg() const { return IsVarArg; } @@ -2284,6 +2285,12 @@ public: SDValue getCallee() const { return getOperand(1); } unsigned getNumArgs() const { return (getNumOperands() - 2) / 2; } + unsigned getNumFixedArgs() const { + if (isVarArg()) + return NumFixedArgs; + else + return getNumArgs(); + } SDValue getArg(unsigned i) const { return getOperand(2+2*i); } SDValue getArgFlagsVal(unsigned i) const { return getOperand(3+2*i); diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 9b2d4afc92e..05f30e2a365 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1122,9 +1122,9 @@ public: typedef std::vector ArgListTy; virtual std::pair LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, - bool isVarArg, bool isInreg, unsigned CallingConv, - bool isTailCall, SDValue Callee, ArgListTy &Args, - SelectionDAG &DAG, DebugLoc dl); + bool isVarArg, bool isInreg, unsigned NumFixedArgs, + unsigned CallingConv, bool isTailCall, SDValue Callee, + ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl); /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a /// memcpy. This can be used by targets to provide code sequences for cases diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index ef365e66e61..1413d9552d0 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1900,7 +1900,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, const Type *RetTy = Node->getValueType(0).getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - CallingConv::C, false, Callee, Args, DAG, + 0, CallingConv::C, false, Callee, Args, DAG, Node->getDebugLoc()); // Legalize the call sequence, starting with the chain. This will advance @@ -2305,7 +2305,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, TargetLowering::ArgListTy Args; std::pair CallResult = TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy, - false, false, false, false, CallingConv::C, false, + false, false, false, false, 0, CallingConv::C, false, DAG.getExternalSymbol("abort", TLI.getPointerTy()), Args, DAG, dl); Results.push_back(CallResult.second); diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index 00d71e1a4fe..3135a445431 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -1006,7 +1006,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const Type *RetTy = RetVT.getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, - false, CallingConv::C, false, Callee, Args, DAG, dl); + false, 0, CallingConv::C, false, Callee, Args, DAG, dl); return CallInfo.first; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 0342f672462..c8f4b520ff1 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3375,7 +3375,7 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, - false, false, false, false, CallingConv::C, false, + false, false, false, false, 0, CallingConv::C, false, getExternalSymbol("memcpy", TLI.getPointerTy()), Args, *this, dl); return CallResult.second; @@ -3421,7 +3421,7 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, - false, false, false, false, CallingConv::C, false, + false, false, false, false, 0, CallingConv::C, false, getExternalSymbol("memmove", TLI.getPointerTy()), Args, *this, dl); return CallResult.second; @@ -3473,7 +3473,7 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, // FIXME: pass in DebugLoc std::pair CallResult = TLI.LowerCallTo(Chain, Type::VoidTy, - false, false, false, false, CallingConv::C, false, + false, false, false, false, 0, CallingConv::C, false, getExternalSymbol("memset", TLI.getPointerTy()), Args, *this, dl); return CallResult.second; @@ -3605,7 +3605,8 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, SDValue SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, bool IsTailCall, bool IsInreg, SDVTList VTs, - const SDValue *Operands, unsigned NumOperands) { + const SDValue *Operands, unsigned NumOperands, + unsigned NumFixedArgs) { // Do not include isTailCall in the folding set profile. FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); @@ -3621,7 +3622,7 @@ SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, } SDNode *N = NodeAllocator.Allocate(); new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, - VTs, Operands, NumOperands); + VTs, Operands, NumOperands, NumFixedArgs); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDValue(N, 0); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index ca1cebc9225..260911e3b99 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -4416,7 +4416,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, TLI.LowerCallTo(getRoot(), CS.getType(), CS.paramHasAttr(0, Attribute::SExt), CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), - CS.paramHasAttr(0, Attribute::InReg), + CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), CS.getCallingConv(), IsTailCall && PerformTailCallOpt, Callee, Args, DAG, getCurDebugLoc()); @@ -5468,7 +5468,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) { std::pair Result = TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false, - CallingConv::C, PerformTailCallOpt, + 0, CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG, getCurDebugLoc()); setValue(&I, Result.first); // Pointers always fit in registers @@ -5484,7 +5484,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { MVT IntPtr = TLI.getPointerTy(); std::pair Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false, - CallingConv::C, PerformTailCallOpt, + 0, CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("free", IntPtr), Args, DAG, getCurDebugLoc()); DAG.setRoot(Result.second); @@ -5657,7 +5657,7 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, std::pair TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, - bool isInreg, + bool isInreg, unsigned NumFixedArgs, unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { @@ -5755,7 +5755,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, isVarArg, isTailCall, isInreg, DAG.getVTList(&LoweredRetTys[0], LoweredRetTys.size()), - &Ops[0], Ops.size() + &Ops[0], Ops.size(), NumFixedArgs ); Chain = Res.getValue(LoweredRetTys.size() - 1); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 9f847bd834f..41c9ecc43a9 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1159,7 +1159,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, // FIXME: is there useful debug info available here? std::pair CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, - CallingConv::C, false, + 0, CallingConv::C, false, DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); return CallResult.first; } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 7a8837cbb3c..fa0b65609fb 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -365,7 +365,8 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { std::pair AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, - bool isInreg, unsigned CallingConv, + bool isInreg, unsigned NumFixedArgs, + unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h index 0a843c24e71..49253673545 100644 --- a/lib/Target/Alpha/AlphaISelLowering.h +++ b/lib/Target/Alpha/AlphaISelLowering.h @@ -86,9 +86,9 @@ namespace llvm { /// actual call. virtual std::pair LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, - bool isVarArg, bool isInreg, unsigned CC, bool isTailCall, - SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, - DebugLoc dl); + bool isVarArg, bool isInreg, unsigned NumFixedArgs, unsigned CC, + bool isTailCall, SDValue Callee, ArgListTy &Args, + SelectionDAG &DAG, DebugLoc dl); ConstraintType getConstraintType(const std::string &Constraint) const; diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index faaccc3aa64..d8a77766bd5 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -113,7 +113,7 @@ namespace { const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - CallingConv::C, false, Callee, Args, DAG, + 0, CallingConv::C, false, Callee, Args, DAG, Op.getDebugLoc()); return CallInfo.first; diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index f5e82a79a71..c6223451ad9 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -315,7 +315,8 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, std::pair IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, - bool isInreg, unsigned CallingConv, + bool isInreg, unsigned NumFixedArgs, + unsigned CallingConv, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h index c552d13b766..b9c8bf2948c 100644 --- a/lib/Target/IA64/IA64ISelLowering.h +++ b/lib/Target/IA64/IA64ISelLowering.h @@ -62,7 +62,7 @@ namespace llvm { virtual std::pair LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg, - unsigned CC, bool isTailCall, + unsigned NumFixedArgs, unsigned CC, bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index ec1db900b38..3bb0164949a 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -399,7 +399,7 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, const Type *RetTy = RetVT.getTypeForMVT(); std::pair CallInfo = LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, - false, CallingConv::C, false, Callee, Args, DAG, dl); + false, 0, CallingConv::C, false, Callee, Args, DAG, dl); return CallInfo.first; } @@ -1302,7 +1302,8 @@ SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) { // Generate new call with all the operands legal return DAG.getCall(TheCall->getCallingConv(), dl, TheCall->isVarArg(), TheCall->isTailCall(), - TheCall->isInreg(), VTs, &Ops[0], Ops.size()); + TheCall->isInreg(), VTs, &Ops[0], Ops.size(), + TheCall->getNumFixedArgs()); } void PIC16TargetLowering:: diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e863ef1b256..7bb764628ea 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1267,7 +1267,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) std::pair CallResult = LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false, - false, false, CallingConv::C, false, + false, false, 0, CallingConv::C, false, DAG.getExternalSymbol("__trampoline_setup", PtrVT), Args, DAG, dl); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 82e88ad1a45..5a6294a211c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5813,7 +5813,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, Args.push_back(Entry); std::pair CallResult = LowerCallTo(Chain, Type::VoidTy, false, false, false, false, - CallingConv::C, false, + 0, CallingConv::C, false, DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); return CallResult.second; }