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Cleaned up code layout. No functional changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-05-22 21:49:18 +00:00
parent e3d3219f76
commit 6b77ec4156
4 changed files with 1262 additions and 1374 deletions
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856
lib/CodeGen/InstrSched/InstrScheduling.cpp
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File diff suppressed because it is too large Load Diff

462
lib/CodeGen/InstrSched/SchedGraph.cpp
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@ -249,20 +249,21 @@ SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
// Delete and disconnect all in-edges for the node // Delete and disconnect all in-edges for the node
for (SchedGraphNode::iterator I = node->beginInEdges(); for (SchedGraphNode::iterator I = node->beginInEdges();
I != node->endInEdges(); ++I) I != node->endInEdges(); ++I)
{ {
SchedGraphNode* srcNode = (*I)->getSrc(); SchedGraphNode* srcNode = (*I)->getSrc();
srcNode->removeOutEdge(*I); srcNode->removeOutEdge(*I);
delete *I; delete *I;
if (addDummyEdges && if (addDummyEdges &&
srcNode != getRoot() && srcNode != getRoot() &&
srcNode->beginOutEdges() == srcNode->endOutEdges()) srcNode->beginOutEdges() == srcNode->endOutEdges())
{ // srcNode has no more out edges, so add an edge to dummy EXIT node {
assert(node != getLeaf() && "Adding edge that was just removed?"); // srcNode has no more out edges, so add an edge to dummy EXIT node
(void) new SchedGraphEdge(srcNode, getLeaf(), assert(node != getLeaf() && "Adding edge that was just removed?");
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0); (void) new SchedGraphEdge(srcNode, getLeaf(),
} SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
} }
}
node->inEdges.clear(); node->inEdges.clear();
} }
@ -273,20 +274,20 @@ SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
// Delete and disconnect all out-edges for the node // Delete and disconnect all out-edges for the node
for (SchedGraphNode::iterator I = node->beginOutEdges(); for (SchedGraphNode::iterator I = node->beginOutEdges();
I != node->endOutEdges(); ++I) I != node->endOutEdges(); ++I)
{ {
SchedGraphNode* sinkNode = (*I)->getSink(); SchedGraphNode* sinkNode = (*I)->getSink();
sinkNode->removeInEdge(*I); sinkNode->removeInEdge(*I);
delete *I; delete *I;
if (addDummyEdges && if (addDummyEdges &&
sinkNode != getLeaf() && sinkNode != getLeaf() &&
sinkNode->beginInEdges() == sinkNode->endInEdges()) sinkNode->beginInEdges() == sinkNode->endInEdges())
{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
assert(node != getRoot() && "Adding edge that was just removed?"); assert(node != getRoot() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(getRoot(), sinkNode, (void) new SchedGraphEdge(getRoot(), sinkNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
}
} }
}
node->outEdges.clear(); node->outEdges.clear();
} }
@ -305,16 +306,16 @@ SchedGraph::addDummyEdges()
assert(graphRoot->outEdges.size() == 0); assert(graphRoot->outEdges.size() == 0);
for (const_iterator I=begin(); I != end(); ++I) for (const_iterator I=begin(); I != end(); ++I)
{ {
SchedGraphNode* node = (*I).second; SchedGraphNode* node = (*I).second;
assert(node != graphRoot && node != graphLeaf); assert(node != graphRoot && node != graphLeaf);
if (node->beginInEdges() == node->endInEdges()) if (node->beginInEdges() == node->endInEdges())
(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
if (node->beginOutEdges() == node->endOutEdges()) if (node->beginOutEdges() == node->endOutEdges())
(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
} }
} }
@ -343,65 +344,65 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
// Use a latency of 0 because we only need to prevent out-of-order issue. // Use a latency of 0 because we only need to prevent out-of-order issue.
// //
for (unsigned i = termMvec.size(); i > first+1; --i) for (unsigned i = termMvec.size(); i > first+1; --i)
{ {
SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]); SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
assert(toNode && "No node for instr generated for branch/ret?"); assert(toNode && "No node for instr generated for branch/ret?");
for (unsigned j = i-1; j != 0; --j) for (unsigned j = i-1; j != 0; --j)
if (mii.isBranch(termMvec[j-1]->getOpCode()) || if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
mii.isReturn(termMvec[j-1]->getOpCode())) mii.isReturn(termMvec[j-1]->getOpCode()))
{ {
SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]); SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
assert(brNode && "No node for instr generated for branch/ret?"); assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
break; // only one incoming edge is enough break; // only one incoming edge is enough
} }
} }
// Add CD edges from each instruction preceding the first branch // Add CD edges from each instruction preceding the first branch
// to the first branch. Use a latency of 0 as above. // to the first branch. Use a latency of 0 as above.
// //
for (unsigned i = first; i != 0; --i) for (unsigned i = first; i != 0; --i)
{ {
SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]); SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
assert(fromNode && "No node for instr generated for branch?"); assert(fromNode && "No node for instr generated for branch?");
(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
} }
// Now add CD edges to the first branch instruction in the sequence from // Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
for (unsigned i=0, N=MBB.size(); i < N; i++) for (unsigned i=0, N=MBB.size(); i < N; i++)
{
if (MBB[i] == termMvec[first]) // reached the first branch
break;
SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
// If we find any other machine instructions (other than due to
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++)
{ {
if (MBB[i] == termMvec[first]) // reached the first branch SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
break; assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
// If we find any other machine instructions (other than due to
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++)
{
SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
} }
}
} }
static const int SG_LOAD_REF = 0; static const int SG_LOAD_REF = 0;
@ -437,24 +438,24 @@ SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>. // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
// //
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
{
MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
: mii.isLoad(fromOpCode)? SG_LOAD_REF
: SG_STORE_REF;
for (unsigned jm=im+1; jm < NM; jm++)
{ {
MachineOpCode fromOpCode = memNodeVec[im]->getOpCode(); MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
int fromType = mii.isCall(fromOpCode)? SG_CALL_REF int toType = mii.isCall(toOpCode)? SG_CALL_REF
: mii.isLoad(fromOpCode)? SG_LOAD_REF : mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF; : SG_STORE_REF;
for (unsigned jm=im+1; jm < NM; jm++)
{
MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
int toType = mii.isCall(toOpCode)? SG_CALL_REF
: mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF;
if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF) if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm], (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
SchedGraphEdge::MemoryDep, SchedGraphEdge::MemoryDep,
SG_DepOrderArray[fromType][toType], 1); SG_DepOrderArray[fromType][toType], 1);
}
} }
}
} }
// Add edges from/to CC reg instrs to/from call instrs. // Add edges from/to CC reg instrs to/from call instrs.
@ -484,24 +485,23 @@ SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
int lastCallNodeIdx = -1; int lastCallNodeIdx = -1;
for (unsigned i=0, N=bbMvec.size(); i < N; i++) for (unsigned i=0, N=bbMvec.size(); i < N; i++)
if (mii.isCall(bbMvec[i]->getOpCode())) if (mii.isCall(bbMvec[i]->getOpCode()))
{ {
++lastCallNodeIdx; ++lastCallNodeIdx;
for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx) for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i]) if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
break; break;
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?"); assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
} } else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
else if (mii.isCCInstr(bbMvec[i]->getOpCode())) // Add incoming/outgoing edges from/to preceding/later calls
{ // Add incoming/outgoing edges from/to preceding/later calls SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]); int j=0;
int j=0; for ( ; j <= lastCallNodeIdx; j++)
for ( ; j <= lastCallNodeIdx; j++) (void) new SchedGraphEdge(callNodeVec[j], ccNode,
(void) new SchedGraphEdge(callNodeVec[j], ccNode, MachineCCRegsRID, 0);
MachineCCRegsRID, 0); for ( ; j < (int) callNodeVec.size(); j++)
for ( ; j < (int) callNodeVec.size(); j++) (void) new SchedGraphEdge(ccNode, callNodeVec[j],
(void) new SchedGraphEdge(ccNode, callNodeVec[j], MachineCCRegsRID, 0);
MachineCCRegsRID, 0); }
}
} }
@ -517,47 +517,43 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
// //
for (RegToRefVecMap::iterator I = regToRefVecMap.begin(); for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
I != regToRefVecMap.end(); ++I) I != regToRefVecMap.end(); ++I)
{ {
int regNum = (*I).first; int regNum = (*I).first;
RefVec& regRefVec = (*I).second; RefVec& regRefVec = (*I).second;
// regRefVec is ordered by control flow order in the basic block // regRefVec is ordered by control flow order in the basic block
for (unsigned i=0; i < regRefVec.size(); ++i) for (unsigned i=0; i < regRefVec.size(); ++i) {
{ SchedGraphNode* node = regRefVec[i].first;
SchedGraphNode* node = regRefVec[i].first; unsigned int opNum = regRefVec[i].second;
unsigned int opNum = regRefVec[i].second; bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
bool isDef = node->getMachineInstr()->operandIsDefined(opNum); bool isDefAndUse =
bool isDefAndUse = node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
for (unsigned p=0; p < i; ++p) for (unsigned p=0; p < i; ++p) {
{ SchedGraphNode* prevNode = regRefVec[p].first;
SchedGraphNode* prevNode = regRefVec[p].first; if (prevNode != node) {
if (prevNode != node) unsigned int prevOpNum = regRefVec[p].second;
{ bool prevIsDef =
unsigned int prevOpNum = regRefVec[p].second; prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
bool prevIsDef = bool prevIsDefAndUse =
prevNode->getMachineInstr()->operandIsDefined(prevOpNum); prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
bool prevIsDefAndUse = if (isDef) {
prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum); if (prevIsDef)
if (isDef) new SchedGraphEdge(prevNode, node, regNum,
{ SchedGraphEdge::OutputDep);
if (prevIsDef) if (!prevIsDef || prevIsDefAndUse)
new SchedGraphEdge(prevNode, node, regNum, new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::OutputDep); SchedGraphEdge::AntiDep);
if (!prevIsDef || prevIsDefAndUse) }
new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::AntiDep);
}
if (prevIsDef) if (prevIsDef)
if (!isDef || isDefAndUse) if (!isDef || isDefAndUse)
new SchedGraphEdge(prevNode, node, regNum, new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::TrueDep); SchedGraphEdge::TrueDep);
}
}
} }
}
} }
}
} }
@ -578,29 +574,28 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
// Add true or output dep edges from all def nodes before refNode in BB. // Add true or output dep edges from all def nodes before refNode in BB.
// Add anti or output dep edges to all def nodes after refNode. // Add anti or output dep edges to all def nodes after refNode.
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
{ {
if ((*I).first == refNode) if ((*I).first == refNode)
continue; // Dont add any self-loops continue; // Dont add any self-loops
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
{ // (*).first is before refNode // (*).first is before refNode
if (refNodeIsDef) if (refNodeIsDef)
(void) new SchedGraphEdge((*I).first, refNode, defValue, (void) new SchedGraphEdge((*I).first, refNode, defValue,
SchedGraphEdge::OutputDep); SchedGraphEdge::OutputDep);
if (refNodeIsUse) if (refNodeIsUse)
(void) new SchedGraphEdge((*I).first, refNode, defValue, (void) new SchedGraphEdge((*I).first, refNode, defValue,
SchedGraphEdge::TrueDep); SchedGraphEdge::TrueDep);
} } else {
else // (*).first is after refNode
{ // (*).first is after refNode if (refNodeIsDef)
if (refNodeIsDef) (void) new SchedGraphEdge(refNode, (*I).first, defValue,
(void) new SchedGraphEdge(refNode, (*I).first, defValue, SchedGraphEdge::OutputDep);
SchedGraphEdge::OutputDep); if (refNodeIsUse)
if (refNodeIsUse) (void) new SchedGraphEdge(refNode, (*I).first, defValue,
(void) new SchedGraphEdge(refNode, (*I).first, defValue, SchedGraphEdge::AntiDep);
SchedGraphEdge::AntiDep);
}
} }
}
} }
@ -616,35 +611,35 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
// Add edges for all operands of the machine instruction. // Add edges for all operands of the machine instruction.
// //
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
switch (MI.getOperandType(i))
{ {
switch (MI.getOperandType(i)) case MachineOperand::MO_VirtualRegister:
{ case MachineOperand::MO_CCRegister:
case MachineOperand::MO_VirtualRegister: if (const Instruction* srcI =
case MachineOperand::MO_CCRegister: dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
if (const Instruction* srcI = {
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue())) ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
{ if (I != valueToDefVecMap.end())
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); addEdgesForValue(node, I->second, srcI,
if (I != valueToDefVecMap.end()) MI.operandIsDefined(i),
addEdgesForValue(node, I->second, srcI, MI.operandIsDefinedAndUsed(i), target);
MI.operandIsDefined(i), }
MI.operandIsDefinedAndUsed(i), target); break;
}
break;
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_PCRelativeDisp:
break; // nothing to do for immediate fields break; // nothing to do for immediate fields
default: default:
assert(0 && "Unknown machine operand type in SchedGraph builder"); assert(0 && "Unknown machine operand type in SchedGraph builder");
break; break;
}
} }
}
// Add edges for values implicitly used by the machine instruction. // Add edges for values implicitly used by the machine instruction.
// Examples include function arguments to a Call instructions or the return // Examples include function arguments to a Call instructions or the return
@ -655,13 +650,13 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
MI.implicitRefIsDefinedAndUsed(i)) MI.implicitRefIsDefinedAndUsed(i))
if (const Instruction *srcI = if (const Instruction *srcI =
dyn_cast_or_null<Instruction>(MI.getImplicitRef(i))) dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
{ {
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end()) if (I != valueToDefVecMap.end())
addEdgesForValue(node, I->second, srcI, addEdgesForValue(node, I->second, srcI,
MI.implicitRefIsDefined(i), MI.implicitRefIsDefined(i),
MI.implicitRefIsDefinedAndUsed(i), target); MI.implicitRefIsDefinedAndUsed(i), target);
} }
} }
@ -683,32 +678,32 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// //
const MachineInstr& minstr = *node->getMachineInstr(); const MachineInstr& minstr = *node->getMachineInstr();
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++) for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
{
const MachineOperand& mop = minstr.getOperand(i);
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.getType() == MachineOperand::MO_MachineRegister)
{ {
const MachineOperand& mop = minstr.getOperand(i); int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
// if this references a register other than the hardwired regToRefVecMap[mop.getMachineRegNum()]
// "zero" register, record the reference. .push_back(std::make_pair(node, i));
if (mop.getType() == MachineOperand::MO_MachineRegister) continue; // nothing more to do
{
int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getMachineRegNum()].push_back(
std::make_pair(node, i));
continue; // nothing more to do
}
// ignore all other non-def operands
if (! minstr.operandIsDefined(i))
continue;
// We must be defining a value.
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
} }
// ignore all other non-def operands
if (! minstr.operandIsDefined(i))
continue;
// We must be defining a value.
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
}
// //
// Collect value defs. for implicit operands. The interface to extract // Collect value defs. for implicit operands. The interface to extract
@ -903,18 +898,17 @@ std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
if (node.getMachineInstr() == NULL) if (node.getMachineInstr() == NULL)
os << "(Dummy node)\n"; os << "(Dummy node)\n";
else else {
{ os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
os << *node.getMachineInstr() << "\n" << std::string(12, ' '); os << node.inEdges.size() << " Incoming Edges:\n";
os << node.inEdges.size() << " Incoming Edges:\n"; for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
for (unsigned i=0, N=node.inEdges.size(); i < N; i++) os << std::string(16, ' ') << *node.inEdges[i];
os << std::string(16, ' ') << *node.inEdges[i];
os << std::string(12, ' ') << node.outEdges.size() os << std::string(12, ' ') << node.outEdges.size()
<< " Outgoing Edges:\n"; << " Outgoing Edges:\n";
for (unsigned i=0, N=node.outEdges.size(); i < N; i++) for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
os << std::string(16, ' ') << *node.outEdges[i]; os << std::string(16, ' ') << *node.outEdges[i];
} }
return os; return os;
} }

856
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
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File diff suppressed because it is too large Load Diff

462
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
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@ -249,20 +249,21 @@ SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
// Delete and disconnect all in-edges for the node // Delete and disconnect all in-edges for the node
for (SchedGraphNode::iterator I = node->beginInEdges(); for (SchedGraphNode::iterator I = node->beginInEdges();
I != node->endInEdges(); ++I) I != node->endInEdges(); ++I)
{ {
SchedGraphNode* srcNode = (*I)->getSrc(); SchedGraphNode* srcNode = (*I)->getSrc();
srcNode->removeOutEdge(*I); srcNode->removeOutEdge(*I);
delete *I; delete *I;
if (addDummyEdges && if (addDummyEdges &&
srcNode != getRoot() && srcNode != getRoot() &&
srcNode->beginOutEdges() == srcNode->endOutEdges()) srcNode->beginOutEdges() == srcNode->endOutEdges())
{ // srcNode has no more out edges, so add an edge to dummy EXIT node {
assert(node != getLeaf() && "Adding edge that was just removed?"); // srcNode has no more out edges, so add an edge to dummy EXIT node
(void) new SchedGraphEdge(srcNode, getLeaf(), assert(node != getLeaf() && "Adding edge that was just removed?");
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0); (void) new SchedGraphEdge(srcNode, getLeaf(),
} SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
} }
}
node->inEdges.clear(); node->inEdges.clear();
} }
@ -273,20 +274,20 @@ SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
// Delete and disconnect all out-edges for the node // Delete and disconnect all out-edges for the node
for (SchedGraphNode::iterator I = node->beginOutEdges(); for (SchedGraphNode::iterator I = node->beginOutEdges();
I != node->endOutEdges(); ++I) I != node->endOutEdges(); ++I)
{ {
SchedGraphNode* sinkNode = (*I)->getSink(); SchedGraphNode* sinkNode = (*I)->getSink();
sinkNode->removeInEdge(*I); sinkNode->removeInEdge(*I);
delete *I; delete *I;
if (addDummyEdges && if (addDummyEdges &&
sinkNode != getLeaf() && sinkNode != getLeaf() &&
sinkNode->beginInEdges() == sinkNode->endInEdges()) sinkNode->beginInEdges() == sinkNode->endInEdges())
{ //sinkNode has no more in edges, so add an edge from dummy ENTRY node { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
assert(node != getRoot() && "Adding edge that was just removed?"); assert(node != getRoot() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(getRoot(), sinkNode, (void) new SchedGraphEdge(getRoot(), sinkNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
}
} }
}
node->outEdges.clear(); node->outEdges.clear();
} }
@ -305,16 +306,16 @@ SchedGraph::addDummyEdges()
assert(graphRoot->outEdges.size() == 0); assert(graphRoot->outEdges.size() == 0);
for (const_iterator I=begin(); I != end(); ++I) for (const_iterator I=begin(); I != end(); ++I)
{ {
SchedGraphNode* node = (*I).second; SchedGraphNode* node = (*I).second;
assert(node != graphRoot && node != graphLeaf); assert(node != graphRoot && node != graphLeaf);
if (node->beginInEdges() == node->endInEdges()) if (node->beginInEdges() == node->endInEdges())
(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
if (node->beginOutEdges() == node->endOutEdges()) if (node->beginOutEdges() == node->endOutEdges())
(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
} }
} }
@ -343,65 +344,65 @@ SchedGraph::addCDEdges(const TerminatorInst* term,
// Use a latency of 0 because we only need to prevent out-of-order issue. // Use a latency of 0 because we only need to prevent out-of-order issue.
// //
for (unsigned i = termMvec.size(); i > first+1; --i) for (unsigned i = termMvec.size(); i > first+1; --i)
{ {
SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]); SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
assert(toNode && "No node for instr generated for branch/ret?"); assert(toNode && "No node for instr generated for branch/ret?");
for (unsigned j = i-1; j != 0; --j) for (unsigned j = i-1; j != 0; --j)
if (mii.isBranch(termMvec[j-1]->getOpCode()) || if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
mii.isReturn(termMvec[j-1]->getOpCode())) mii.isReturn(termMvec[j-1]->getOpCode()))
{ {
SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]); SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
assert(brNode && "No node for instr generated for branch/ret?"); assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
break; // only one incoming edge is enough break; // only one incoming edge is enough
} }
} }
// Add CD edges from each instruction preceding the first branch // Add CD edges from each instruction preceding the first branch
// to the first branch. Use a latency of 0 as above. // to the first branch. Use a latency of 0 as above.
// //
for (unsigned i = first; i != 0; --i) for (unsigned i = first; i != 0; --i)
{ {
SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]); SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
assert(fromNode && "No node for instr generated for branch?"); assert(fromNode && "No node for instr generated for branch?");
(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep, (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
} }
// Now add CD edges to the first branch instruction in the sequence from // Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again. // all preceding instructions in the basic block. Use 0 latency again.
// //
for (unsigned i=0, N=MBB.size(); i < N; i++) for (unsigned i=0, N=MBB.size(); i < N; i++)
{
if (MBB[i] == termMvec[first]) // reached the first branch
break;
SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
// If we find any other machine instructions (other than due to
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++)
{ {
if (MBB[i] == termMvec[first]) // reached the first branch SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
break; assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0); SchedGraphEdge::NonDataDep, 0);
// If we find any other machine instructions (other than due to
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++)
{
SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
} }
}
} }
static const int SG_LOAD_REF = 0; static const int SG_LOAD_REF = 0;
@ -437,24 +438,24 @@ SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>. // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
// //
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
{
MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
: mii.isLoad(fromOpCode)? SG_LOAD_REF
: SG_STORE_REF;
for (unsigned jm=im+1; jm < NM; jm++)
{ {
MachineOpCode fromOpCode = memNodeVec[im]->getOpCode(); MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
int fromType = mii.isCall(fromOpCode)? SG_CALL_REF int toType = mii.isCall(toOpCode)? SG_CALL_REF
: mii.isLoad(fromOpCode)? SG_LOAD_REF : mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF; : SG_STORE_REF;
for (unsigned jm=im+1; jm < NM; jm++)
{
MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
int toType = mii.isCall(toOpCode)? SG_CALL_REF
: mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF;
if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF) if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm], (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
SchedGraphEdge::MemoryDep, SchedGraphEdge::MemoryDep,
SG_DepOrderArray[fromType][toType], 1); SG_DepOrderArray[fromType][toType], 1);
}
} }
}
} }
// Add edges from/to CC reg instrs to/from call instrs. // Add edges from/to CC reg instrs to/from call instrs.
@ -484,24 +485,23 @@ SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
int lastCallNodeIdx = -1; int lastCallNodeIdx = -1;
for (unsigned i=0, N=bbMvec.size(); i < N; i++) for (unsigned i=0, N=bbMvec.size(); i < N; i++)
if (mii.isCall(bbMvec[i]->getOpCode())) if (mii.isCall(bbMvec[i]->getOpCode()))
{ {
++lastCallNodeIdx; ++lastCallNodeIdx;
for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx) for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i]) if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
break; break;
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?"); assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
} } else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
else if (mii.isCCInstr(bbMvec[i]->getOpCode())) // Add incoming/outgoing edges from/to preceding/later calls
{ // Add incoming/outgoing edges from/to preceding/later calls SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]); int j=0;
int j=0; for ( ; j <= lastCallNodeIdx; j++)
for ( ; j <= lastCallNodeIdx; j++) (void) new SchedGraphEdge(callNodeVec[j], ccNode,
(void) new SchedGraphEdge(callNodeVec[j], ccNode, MachineCCRegsRID, 0);
MachineCCRegsRID, 0); for ( ; j < (int) callNodeVec.size(); j++)
for ( ; j < (int) callNodeVec.size(); j++) (void) new SchedGraphEdge(ccNode, callNodeVec[j],
(void) new SchedGraphEdge(ccNode, callNodeVec[j], MachineCCRegsRID, 0);
MachineCCRegsRID, 0); }
}
} }
@ -517,47 +517,43 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
// //
for (RegToRefVecMap::iterator I = regToRefVecMap.begin(); for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
I != regToRefVecMap.end(); ++I) I != regToRefVecMap.end(); ++I)
{ {
int regNum = (*I).first; int regNum = (*I).first;
RefVec& regRefVec = (*I).second; RefVec& regRefVec = (*I).second;
// regRefVec is ordered by control flow order in the basic block // regRefVec is ordered by control flow order in the basic block
for (unsigned i=0; i < regRefVec.size(); ++i) for (unsigned i=0; i < regRefVec.size(); ++i) {
{ SchedGraphNode* node = regRefVec[i].first;
SchedGraphNode* node = regRefVec[i].first; unsigned int opNum = regRefVec[i].second;
unsigned int opNum = regRefVec[i].second; bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
bool isDef = node->getMachineInstr()->operandIsDefined(opNum); bool isDefAndUse =
bool isDefAndUse = node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
for (unsigned p=0; p < i; ++p) for (unsigned p=0; p < i; ++p) {
{ SchedGraphNode* prevNode = regRefVec[p].first;
SchedGraphNode* prevNode = regRefVec[p].first; if (prevNode != node) {
if (prevNode != node) unsigned int prevOpNum = regRefVec[p].second;
{ bool prevIsDef =
unsigned int prevOpNum = regRefVec[p].second; prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
bool prevIsDef = bool prevIsDefAndUse =
prevNode->getMachineInstr()->operandIsDefined(prevOpNum); prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
bool prevIsDefAndUse = if (isDef) {
prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum); if (prevIsDef)
if (isDef) new SchedGraphEdge(prevNode, node, regNum,
{ SchedGraphEdge::OutputDep);
if (prevIsDef) if (!prevIsDef || prevIsDefAndUse)
new SchedGraphEdge(prevNode, node, regNum, new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::OutputDep); SchedGraphEdge::AntiDep);
if (!prevIsDef || prevIsDefAndUse) }
new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::AntiDep);
}
if (prevIsDef) if (prevIsDef)
if (!isDef || isDefAndUse) if (!isDef || isDefAndUse)
new SchedGraphEdge(prevNode, node, regNum, new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::TrueDep); SchedGraphEdge::TrueDep);
}
}
} }
}
} }
}
} }
@ -578,29 +574,28 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
// Add true or output dep edges from all def nodes before refNode in BB. // Add true or output dep edges from all def nodes before refNode in BB.
// Add anti or output dep edges to all def nodes after refNode. // Add anti or output dep edges to all def nodes after refNode.
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
{ {
if ((*I).first == refNode) if ((*I).first == refNode)
continue; // Dont add any self-loops continue; // Dont add any self-loops
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
{ // (*).first is before refNode // (*).first is before refNode
if (refNodeIsDef) if (refNodeIsDef)
(void) new SchedGraphEdge((*I).first, refNode, defValue, (void) new SchedGraphEdge((*I).first, refNode, defValue,
SchedGraphEdge::OutputDep); SchedGraphEdge::OutputDep);
if (refNodeIsUse) if (refNodeIsUse)
(void) new SchedGraphEdge((*I).first, refNode, defValue, (void) new SchedGraphEdge((*I).first, refNode, defValue,
SchedGraphEdge::TrueDep); SchedGraphEdge::TrueDep);
} } else {
else // (*).first is after refNode
{ // (*).first is after refNode if (refNodeIsDef)
if (refNodeIsDef) (void) new SchedGraphEdge(refNode, (*I).first, defValue,
(void) new SchedGraphEdge(refNode, (*I).first, defValue, SchedGraphEdge::OutputDep);
SchedGraphEdge::OutputDep); if (refNodeIsUse)
if (refNodeIsUse) (void) new SchedGraphEdge(refNode, (*I).first, defValue,
(void) new SchedGraphEdge(refNode, (*I).first, defValue, SchedGraphEdge::AntiDep);
SchedGraphEdge::AntiDep);
}
} }
}
} }
@ -616,35 +611,35 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
// Add edges for all operands of the machine instruction. // Add edges for all operands of the machine instruction.
// //
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
switch (MI.getOperandType(i))
{ {
switch (MI.getOperandType(i)) case MachineOperand::MO_VirtualRegister:
{ case MachineOperand::MO_CCRegister:
case MachineOperand::MO_VirtualRegister: if (const Instruction* srcI =
case MachineOperand::MO_CCRegister: dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
if (const Instruction* srcI = {
dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue())) ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
{ if (I != valueToDefVecMap.end())
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); addEdgesForValue(node, I->second, srcI,
if (I != valueToDefVecMap.end()) MI.operandIsDefined(i),
addEdgesForValue(node, I->second, srcI, MI.operandIsDefinedAndUsed(i), target);
MI.operandIsDefined(i), }
MI.operandIsDefinedAndUsed(i), target); break;
}
break;
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_PCRelativeDisp:
break; // nothing to do for immediate fields break; // nothing to do for immediate fields
default: default:
assert(0 && "Unknown machine operand type in SchedGraph builder"); assert(0 && "Unknown machine operand type in SchedGraph builder");
break; break;
}
} }
}
// Add edges for values implicitly used by the machine instruction. // Add edges for values implicitly used by the machine instruction.
// Examples include function arguments to a Call instructions or the return // Examples include function arguments to a Call instructions or the return
@ -655,13 +650,13 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
MI.implicitRefIsDefinedAndUsed(i)) MI.implicitRefIsDefinedAndUsed(i))
if (const Instruction *srcI = if (const Instruction *srcI =
dyn_cast_or_null<Instruction>(MI.getImplicitRef(i))) dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
{ {
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI); ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end()) if (I != valueToDefVecMap.end())
addEdgesForValue(node, I->second, srcI, addEdgesForValue(node, I->second, srcI,
MI.implicitRefIsDefined(i), MI.implicitRefIsDefined(i),
MI.implicitRefIsDefinedAndUsed(i), target); MI.implicitRefIsDefinedAndUsed(i), target);
} }
} }
@ -683,32 +678,32 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// //
const MachineInstr& minstr = *node->getMachineInstr(); const MachineInstr& minstr = *node->getMachineInstr();
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++) for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
{
const MachineOperand& mop = minstr.getOperand(i);
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.getType() == MachineOperand::MO_MachineRegister)
{ {
const MachineOperand& mop = minstr.getOperand(i); int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
// if this references a register other than the hardwired regToRefVecMap[mop.getMachineRegNum()]
// "zero" register, record the reference. .push_back(std::make_pair(node, i));
if (mop.getType() == MachineOperand::MO_MachineRegister) continue; // nothing more to do
{
int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getMachineRegNum()].push_back(
std::make_pair(node, i));
continue; // nothing more to do
}
// ignore all other non-def operands
if (! minstr.operandIsDefined(i))
continue;
// We must be defining a value.
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
} }
// ignore all other non-def operands
if (! minstr.operandIsDefined(i))
continue;
// We must be defining a value.
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
}
// //
// Collect value defs. for implicit operands. The interface to extract // Collect value defs. for implicit operands. The interface to extract
@ -903,18 +898,17 @@ std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
if (node.getMachineInstr() == NULL) if (node.getMachineInstr() == NULL)
os << "(Dummy node)\n"; os << "(Dummy node)\n";
else else {
{ os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
os << *node.getMachineInstr() << "\n" << std::string(12, ' '); os << node.inEdges.size() << " Incoming Edges:\n";
os << node.inEdges.size() << " Incoming Edges:\n"; for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
for (unsigned i=0, N=node.inEdges.size(); i < N; i++) os << std::string(16, ' ') << *node.inEdges[i];
os << std::string(16, ' ') << *node.inEdges[i];
os << std::string(12, ' ') << node.outEdges.size() os << std::string(12, ' ') << node.outEdges.size()
<< " Outgoing Edges:\n"; << " Outgoing Edges:\n";
for (unsigned i=0, N=node.outEdges.size(); i < N; i++) for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
os << std::string(16, ' ') << *node.outEdges[i]; os << std::string(16, ' ') << *node.outEdges[i];
} }
return os; return os;
} }