mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Cleaned up code layout. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e3d3219f76
commit
6b77ec4156
@ -223,8 +223,7 @@ ScheduleIterator<_NodeType>::skipToNextInstr()
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(*S.groups[cycleNum])[slotNum] == NULL)
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{
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++slotNum;
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if (slotNum == S.nslots)
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{
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if (slotNum == S.nslots) {
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++cycleNum;
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slotNum = 0;
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while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
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@ -239,8 +238,7 @@ ScheduleIterator<_NodeType>&
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ScheduleIterator<_NodeType>::operator++() // Preincrement
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{
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++slotNum;
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if (slotNum == S.nslots)
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{
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if (slotNum == S.nslots) {
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++cycleNum;
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slotNum = 0;
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}
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@ -574,8 +572,8 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
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// If only one instruction can be issued, do so.
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if (maxIssue == 1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if (S.getChoicesForSlot(s).size() > 0)
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{// found the one instruction
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if (S.getChoicesForSlot(s).size() > 0) {
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// found the one instruction
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S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
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return;
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}
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@ -589,26 +587,23 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
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// If all slots have 0 or multiple choices, pick the first slot with
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// choices and use its last instruction (just to avoid shifting the vector).
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unsigned numIssued;
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for (numIssued = 0; numIssued < maxIssue; numIssued++)
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{
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for (numIssued = 0; numIssued < maxIssue; numIssued++) {
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int chosenSlot = -1;
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1)
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{
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1) {
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chosenSlot = (int) s;
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break;
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}
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if (chosenSlot == -1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0)
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{
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0) {
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chosenSlot = (int) s;
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break;
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}
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if (chosenSlot != -1)
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{ // Insert the chosen instr in the chosen slot and
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if (chosenSlot != -1) {
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// Insert the chosen instr in the chosen slot and
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// erase it from all slots.
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const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
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S.scheduleInstr(node, chosenSlot, curTime);
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@ -673,13 +668,12 @@ MarkSuccessorsReady(SchedulingManager& S, const SchedGraphNode* node)
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if (! (*SI)->isDummyNode()
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&& ! S.isScheduled(*SI)
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&& ! S.schedPrio.nodeIsReady(*SI))
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{// successor not scheduled and not marked ready; check *its* preds.
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{
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// successor not scheduled and not marked ready; check *its* preds.
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bool succIsReady = true;
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for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
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if (! (*P)->isDummyNode()
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&& ! S.isScheduled(*P))
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{
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if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) {
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succIsReady = false;
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break;
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}
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@ -710,8 +704,7 @@ FindSlotChoices(SchedulingManager& S,
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unsigned int startSlot = 0;
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InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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for (int s = S.nslots - 1; s >= 0; s--)
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if ((*igroup)[s] != NULL)
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{
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if ((*igroup)[s] != NULL) {
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startSlot = s+1;
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break;
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}
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@ -729,17 +722,14 @@ FindSlotChoices(SchedulingManager& S,
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// we choose them so that subsequent choices will be correctly tested
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// for feasibility, w.r.t. higher priority choices for the same cycle.
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//
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while (S.getNumChoices() < S.nslots - startSlot)
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{
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while (S.getNumChoices() < S.nslots - startSlot) {
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const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
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if (nextNode == NULL)
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break; // no more instructions for this cycle
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if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0)
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{
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if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0) {
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delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
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if (delaySlotInfo != NULL)
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{
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if (delaySlotInfo != NULL) {
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if (indexForBreakingNode < S.nslots)
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// cannot issue a delayed instr in the same cycle as one
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// that breaks the issue group or as another delayed instr
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@ -747,9 +737,7 @@ FindSlotChoices(SchedulingManager& S,
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else
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indexForDelayedInstr = S.getNumChoices();
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}
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}
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else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode()))
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{
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} else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode())) {
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if (indexForBreakingNode < S.nslots)
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// have a breaking instruction already so throw this one away
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nextNode = NULL;
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@ -757,12 +745,10 @@ FindSlotChoices(SchedulingManager& S,
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indexForBreakingNode = S.getNumChoices();
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}
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if (nextNode != NULL)
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{
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if (nextNode != NULL) {
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S.addChoice(nextNode);
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if (S.schedInfo.isSingleIssue(nextNode->getOpCode()))
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{
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if (S.schedInfo.isSingleIssue(nextNode->getOpCode())) {
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assert(S.getNumChoices() == 1 &&
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"Prioritizer returned invalid instr for this cycle!");
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break;
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@ -786,8 +772,7 @@ FindSlotChoices(SchedulingManager& S,
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{ // No instructions that break the issue group or that have delay slots.
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// This is the common case, so handle it separately for efficiency.
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if (S.getNumChoices() == 1)
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{
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if (S.getNumChoices() == 1) {
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MachineOpCode opCode = S.getChoice(0)->getOpCode();
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unsigned int s;
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for (s=startSlot; s < S.nslots; s++)
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@ -795,20 +780,15 @@ FindSlotChoices(SchedulingManager& S,
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break;
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assert(s < S.nslots && "No feasible slot for this opCode?");
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S.addChoiceToSlot(s, S.getChoice(0));
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}
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else
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{
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for (unsigned i=0; i < S.getNumChoices(); i++)
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{
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} else {
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for (unsigned i=0; i < S.getNumChoices(); i++) {
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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for (unsigned int s=startSlot; s < S.nslots; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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S.addChoiceToSlot(s, S.getChoice(i));
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}
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}
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}
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else if (indexForDelayedInstr < S.nslots)
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{
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} else if (indexForDelayedInstr < S.nslots) {
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// There is an instruction that needs delay slots.
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// Try to assign that instruction to a higher slot than any other
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// instructions in the group, so that its delay slots can go
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@ -829,23 +809,20 @@ FindSlotChoices(SchedulingManager& S,
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// Find the last possible slot for the delayed instruction that leaves
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// at least `d' slots vacant after it (d = #delay slots)
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for (int s = S.nslots-ndelays-1; s >= (int) startSlot; s--)
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if (S.schedInfo.instrCanUseSlot(delayOpCode, s))
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{
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if (S.schedInfo.instrCanUseSlot(delayOpCode, s)) {
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delayedNodeSlot = s;
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break;
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}
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highestSlotUsed = -1;
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for (unsigned i=0; i < S.getNumChoices() - 1; i++)
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{
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for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
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// Try to assign every other instruction to a lower numbered
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// slot than delayedNodeSlot.
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MachineOpCode opCode =S.getChoice(i)->getOpCode();
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bool noSlotFound = true;
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unsigned int s;
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for (s=startSlot; s < delayedNodeSlot; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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{
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if (S.schedInfo.instrCanUseSlot(opCode, s)) {
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S.addChoiceToSlot(s, S.getChoice(i));
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noSlotFound = false;
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}
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@ -855,8 +832,7 @@ FindSlotChoices(SchedulingManager& S,
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// the next cycle.
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if (noSlotFound)
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for ( ; s < S.nslots; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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{
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if (S.schedInfo.instrCanUseSlot(opCode, s)) {
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S.addChoiceToSlot(s, S.getChoice(i));
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break;
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}
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@ -874,16 +850,14 @@ FindSlotChoices(SchedulingManager& S,
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// slots for the node at the same time.
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cycles_t dcycle = S.getTime();
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unsigned int dslot = highestSlotUsed + 1;
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if (dslot == S.nslots)
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{
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if (dslot == S.nslots) {
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dslot = 0;
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++dcycle;
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}
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delaySlotInfo->recordChosenSlot(dcycle, dslot);
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getDelaySlotInfo = delaySlotInfo;
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}
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else
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{ // There is an instruction that breaks the issue group.
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} else {
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// There is an instruction that breaks the issue group.
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// For such an instruction, assign to the last possible slot in
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// the current group, and then don't assign any other instructions
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// to later slots.
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@ -894,8 +868,7 @@ FindSlotChoices(SchedulingManager& S,
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// Find the last possible slot for this instruction.
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for (int s = S.nslots-1; s >= (int) startSlot; s--)
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if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s))
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{
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if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s)) {
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breakingSlot = s;
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break;
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}
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@ -916,10 +889,8 @@ FindSlotChoices(SchedulingManager& S,
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bool foundLowerSlot = false;
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nslotsToUse = S.nslots; // May be modified in the loop
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for (unsigned int s=startSlot; s < nslotsToUse; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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{
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if (breakingSlot < S.nslots && s < breakingSlot)
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{
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if (S.schedInfo.instrCanUseSlot(opCode, s)) {
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if (breakingSlot < S.nslots && s < breakingSlot) {
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foundLowerSlot = true;
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nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
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}
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@ -934,19 +905,16 @@ FindSlotChoices(SchedulingManager& S,
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// Assign the breaking instruction (if any) to a single slot
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// Otherwise, just ignore the instruction. It will simply be
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// scheduled in a later cycle.
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if (breakingSlot < S.nslots)
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{
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if (breakingSlot < S.nslots) {
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S.addChoiceToSlot(breakingSlot, breakingNode);
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nslotsToUse = breakingSlot;
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}
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else
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} else
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nslotsToUse = S.nslots;
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// For lower priority instructions than the one that breaks the
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// group, only assign them to slots lower than the breaking slot.
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// Otherwise, just ignore the instruction.
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for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++)
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{
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for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
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MachineOpCode opCode = S.getChoice(i)->getOpCode();
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for (unsigned int s=startSlot; s < nslotsToUse; s++)
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if (S.schedInfo.instrCanUseSlot(opCode, s))
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@ -970,8 +938,7 @@ ChooseOneGroup(SchedulingManager& S)
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// Choose up to `nslots' feasible instructions and their possible slots.
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unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
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while (numIssued == 0)
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{
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while (numIssued == 0) {
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S.updateTime(S.getTime()+1);
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numIssued = FindSlotChoices(S, getDelaySlotInfo);
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}
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@ -982,14 +949,11 @@ ChooseOneGroup(SchedulingManager& S)
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numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
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// Print trace of scheduled instructions before newly ready ones
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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{
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for (cycles_t c = firstCycle; c <= S.getTime(); c++)
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{
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if (SchedDebugLevel >= Sched_PrintSchedTrace) {
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for (cycles_t c = firstCycle; c <= S.getTime(); c++) {
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std::cerr << " Cycle " << (long)c <<" : Scheduled instructions:\n";
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const InstrGroup* igroup = S.isched.getIGroup(c);
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for (unsigned int s=0; s < S.nslots; s++)
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{
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for (unsigned int s=0; s < S.nslots; s++) {
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std::cerr << " ";
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if ((*igroup)[s] != NULL)
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std::cerr << * ((*igroup)[s])->getMachineInstr() << "\n";
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@ -1011,8 +975,7 @@ ForwardListSchedule(SchedulingManager& S)
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S.schedPrio.initialize();
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while ((N = S.schedPrio.getNumReady()) > 0)
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{
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while ((N = S.schedPrio.getNumReady()) > 0) {
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cycles_t nextCycle = S.getTime();
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// Choose one group of instructions for a cycle, plus any delay slot
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@ -1026,12 +989,10 @@ ForwardListSchedule(SchedulingManager& S)
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// Notify the priority manager of scheduled instructions and mark
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// any successors that may now be ready
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//
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for (cycles_t c = nextCycle; c <= S.getTime(); c++)
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{
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for (cycles_t c = nextCycle; c <= S.getTime(); c++) {
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const InstrGroup* igroup = S.isched.getIGroup(c);
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for (unsigned int s=0; s < S.nslots; s++)
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if ((node = (*igroup)[s]) != NULL)
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{
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if ((node = (*igroup)[s]) != NULL) {
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S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
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MarkSuccessorsReady(S, node);
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}
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@ -1092,8 +1053,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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// instruction can be reordered relative to the branch. We simply check
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// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
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//
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if (nodeIsPredecessor)
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{
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if (nodeIsPredecessor) {
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bool onlyCDEdgeToBranch = true;
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for (SchedGraphNode::const_iterator OEI = node->beginOutEdges();
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OEI != node->endOutEdges(); ++OEI)
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@ -1120,14 +1080,13 @@ MarkNodeForDelaySlot(SchedulingManager& S,
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const SchedGraphNode* brNode,
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bool nodeIsPredecessor)
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{
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if (nodeIsPredecessor)
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{ // If node is in the same basic block (i.e., preceeds brNode),
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if (nodeIsPredecessor) {
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// If node is in the same basic block (i.e., preceeds brNode),
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// remove it and all its incident edges from the graph. Make sure we
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// add dummy edges for pred/succ nodes that become entry/exit nodes.
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graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
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}
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else
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{ // If the node was from a target block, add the node to the graph
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} else {
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// If the node was from a target block, add the node to the graph
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// and add a CD edge from brNode to node.
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assert(0 && "NOT IMPLEMENTED YET");
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}
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@ -1173,8 +1132,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
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// Note that this is the most efficient code when only 1 (or even 2)
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// values need to be selected.
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//
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while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
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{
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while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
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unsigned lmin =
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mii.maxLatency(mdelayNodeVec[0]->getOpCode());
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unsigned minIndex = 0;
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@ -1202,6 +1160,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
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//
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static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
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SchedGraphNode* node,
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// FIXME: passing vector BY VALUE!!!
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std::vector<SchedGraphNode*> sdelayNodeVec,
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SchedGraph* graph)
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{
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@ -1234,8 +1193,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
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if (mii.isNop(MBB[i]->getOpCode()))
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if (sdelayNodeVec.size() < ndelays)
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sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
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else
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{
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else {
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nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
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//remove the MI from the Machine Code For Instruction
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@ -1310,8 +1268,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
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// Compute a vector of the nodes chosen for delay slots and then
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// mark delay slots to replace NOPs with these useful instructions.
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//
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if (brInstr != NULL)
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{
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if (brInstr != NULL) {
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SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
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FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
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ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
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@ -1347,11 +1304,9 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
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S.scheduleInstr(brNode, nextSlot, nextTime);
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for (unsigned d=0; d < ndelays; d++)
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{
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for (unsigned d=0; d < ndelays; d++) {
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++nextSlot;
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if (nextSlot == S.nslots)
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{
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if (nextSlot == S.nslots) {
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nextSlot = 0;
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nextTime++;
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}
|
||||
@ -1361,8 +1316,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
// We do *not* check for flow dependences but rely on pipeline
|
||||
// interlocks to resolve them. Machines without interlocks
|
||||
// will require this code to be modified.
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++)
|
||||
{
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++) {
|
||||
const SchedGraphNode* dnode = delayNodeVec[i];
|
||||
if ( ! S.isScheduled(dnode)
|
||||
&& S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
|
||||
@ -1388,12 +1342,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
nextSlot = delayedNodeSlotNum;
|
||||
nextTime = delayedNodeCycle;
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++)
|
||||
if (! S.isScheduled(delayNodeVec[i]))
|
||||
{
|
||||
if (! S.isScheduled(delayNodeVec[i])) {
|
||||
do { // find the next empty slot
|
||||
++nextSlot;
|
||||
if (nextSlot == S.nslots)
|
||||
{
|
||||
if (nextSlot == S.nslots) {
|
||||
nextSlot = 0;
|
||||
nextTime++;
|
||||
}
|
||||
@ -1507,8 +1459,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
|
||||
{
|
||||
SchedGraphSet graphSet(&F, target);
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
|
||||
{
|
||||
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
|
||||
std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
|
||||
graphSet.dump();
|
||||
}
|
||||
@ -1531,8 +1482,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
|
||||
RecordSchedule(MBB, S); // records schedule in BB
|
||||
}
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintMachineCode)
|
||||
{
|
||||
if (SchedDebugLevel >= Sched_PrintMachineCode) {
|
||||
std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
|
||||
MachineFunction::get(&F).dump();
|
||||
}
|
||||
|
@ -257,7 +257,8 @@ SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
|
||||
if (addDummyEdges &&
|
||||
srcNode != getRoot() &&
|
||||
srcNode->beginOutEdges() == srcNode->endOutEdges())
|
||||
{ // srcNode has no more out edges, so add an edge to dummy EXIT node
|
||||
{
|
||||
// srcNode has no more out edges, so add an edge to dummy EXIT node
|
||||
assert(node != getLeaf() && "Adding edge that was just removed?");
|
||||
(void) new SchedGraphEdge(srcNode, getLeaf(),
|
||||
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
|
||||
@ -490,9 +491,8 @@ SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
|
||||
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
|
||||
break;
|
||||
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
|
||||
}
|
||||
else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
|
||||
{ // Add incoming/outgoing edges from/to preceding/later calls
|
||||
} else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
|
||||
// Add incoming/outgoing edges from/to preceding/later calls
|
||||
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
|
||||
int j=0;
|
||||
for ( ; j <= lastCallNodeIdx; j++)
|
||||
@ -522,26 +522,22 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
|
||||
RefVec& regRefVec = (*I).second;
|
||||
|
||||
// regRefVec is ordered by control flow order in the basic block
|
||||
for (unsigned i=0; i < regRefVec.size(); ++i)
|
||||
{
|
||||
for (unsigned i=0; i < regRefVec.size(); ++i) {
|
||||
SchedGraphNode* node = regRefVec[i].first;
|
||||
unsigned int opNum = regRefVec[i].second;
|
||||
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
||||
bool isDefAndUse =
|
||||
node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
|
||||
|
||||
for (unsigned p=0; p < i; ++p)
|
||||
{
|
||||
for (unsigned p=0; p < i; ++p) {
|
||||
SchedGraphNode* prevNode = regRefVec[p].first;
|
||||
if (prevNode != node)
|
||||
{
|
||||
if (prevNode != node) {
|
||||
unsigned int prevOpNum = regRefVec[p].second;
|
||||
bool prevIsDef =
|
||||
prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
|
||||
bool prevIsDefAndUse =
|
||||
prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
|
||||
if (isDef)
|
||||
{
|
||||
if (isDef) {
|
||||
if (prevIsDef)
|
||||
new SchedGraphEdge(prevNode, node, regNum,
|
||||
SchedGraphEdge::OutputDep);
|
||||
@ -582,17 +578,16 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
|
||||
if ((*I).first == refNode)
|
||||
continue; // Dont add any self-loops
|
||||
|
||||
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
|
||||
{ // (*).first is before refNode
|
||||
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
|
||||
// (*).first is before refNode
|
||||
if (refNodeIsDef)
|
||||
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
||||
SchedGraphEdge::OutputDep);
|
||||
if (refNodeIsUse)
|
||||
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
||||
SchedGraphEdge::TrueDep);
|
||||
}
|
||||
else
|
||||
{ // (*).first is after refNode
|
||||
} else {
|
||||
// (*).first is after refNode
|
||||
if (refNodeIsDef)
|
||||
(void) new SchedGraphEdge(refNode, (*I).first, defValue,
|
||||
SchedGraphEdge::OutputDep);
|
||||
@ -692,8 +687,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
||||
{
|
||||
int regNum = mop.getMachineRegNum();
|
||||
if (regNum != target.getRegInfo().getZeroRegNum())
|
||||
regToRefVecMap[mop.getMachineRegNum()].push_back(
|
||||
std::make_pair(node, i));
|
||||
regToRefVecMap[mop.getMachineRegNum()]
|
||||
.push_back(std::make_pair(node, i));
|
||||
continue; // nothing more to do
|
||||
}
|
||||
|
||||
@ -903,8 +898,7 @@ std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
|
||||
|
||||
if (node.getMachineInstr() == NULL)
|
||||
os << "(Dummy node)\n";
|
||||
else
|
||||
{
|
||||
else {
|
||||
os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
|
||||
os << node.inEdges.size() << " Incoming Edges:\n";
|
||||
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
||||
|
@ -223,8 +223,7 @@ ScheduleIterator<_NodeType>::skipToNextInstr()
|
||||
(*S.groups[cycleNum])[slotNum] == NULL)
|
||||
{
|
||||
++slotNum;
|
||||
if (slotNum == S.nslots)
|
||||
{
|
||||
if (slotNum == S.nslots) {
|
||||
++cycleNum;
|
||||
slotNum = 0;
|
||||
while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
|
||||
@ -239,8 +238,7 @@ ScheduleIterator<_NodeType>&
|
||||
ScheduleIterator<_NodeType>::operator++() // Preincrement
|
||||
{
|
||||
++slotNum;
|
||||
if (slotNum == S.nslots)
|
||||
{
|
||||
if (slotNum == S.nslots) {
|
||||
++cycleNum;
|
||||
slotNum = 0;
|
||||
}
|
||||
@ -574,8 +572,8 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
|
||||
// If only one instruction can be issued, do so.
|
||||
if (maxIssue == 1)
|
||||
for (unsigned s=startSlot; s < S.nslots; s++)
|
||||
if (S.getChoicesForSlot(s).size() > 0)
|
||||
{// found the one instruction
|
||||
if (S.getChoicesForSlot(s).size() > 0) {
|
||||
// found the one instruction
|
||||
S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
|
||||
return;
|
||||
}
|
||||
@ -589,26 +587,23 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
|
||||
// If all slots have 0 or multiple choices, pick the first slot with
|
||||
// choices and use its last instruction (just to avoid shifting the vector).
|
||||
unsigned numIssued;
|
||||
for (numIssued = 0; numIssued < maxIssue; numIssued++)
|
||||
{
|
||||
for (numIssued = 0; numIssued < maxIssue; numIssued++) {
|
||||
int chosenSlot = -1;
|
||||
for (unsigned s=startSlot; s < S.nslots; s++)
|
||||
if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1)
|
||||
{
|
||||
if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1) {
|
||||
chosenSlot = (int) s;
|
||||
break;
|
||||
}
|
||||
|
||||
if (chosenSlot == -1)
|
||||
for (unsigned s=startSlot; s < S.nslots; s++)
|
||||
if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0)
|
||||
{
|
||||
if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0) {
|
||||
chosenSlot = (int) s;
|
||||
break;
|
||||
}
|
||||
|
||||
if (chosenSlot != -1)
|
||||
{ // Insert the chosen instr in the chosen slot and
|
||||
if (chosenSlot != -1) {
|
||||
// Insert the chosen instr in the chosen slot and
|
||||
// erase it from all slots.
|
||||
const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
|
||||
S.scheduleInstr(node, chosenSlot, curTime);
|
||||
@ -673,13 +668,12 @@ MarkSuccessorsReady(SchedulingManager& S, const SchedGraphNode* node)
|
||||
if (! (*SI)->isDummyNode()
|
||||
&& ! S.isScheduled(*SI)
|
||||
&& ! S.schedPrio.nodeIsReady(*SI))
|
||||
{// successor not scheduled and not marked ready; check *its* preds.
|
||||
{
|
||||
// successor not scheduled and not marked ready; check *its* preds.
|
||||
|
||||
bool succIsReady = true;
|
||||
for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
|
||||
if (! (*P)->isDummyNode()
|
||||
&& ! S.isScheduled(*P))
|
||||
{
|
||||
if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) {
|
||||
succIsReady = false;
|
||||
break;
|
||||
}
|
||||
@ -710,8 +704,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
unsigned int startSlot = 0;
|
||||
InstrGroup* igroup = S.isched.getIGroup(S.getTime());
|
||||
for (int s = S.nslots - 1; s >= 0; s--)
|
||||
if ((*igroup)[s] != NULL)
|
||||
{
|
||||
if ((*igroup)[s] != NULL) {
|
||||
startSlot = s+1;
|
||||
break;
|
||||
}
|
||||
@ -729,17 +722,14 @@ FindSlotChoices(SchedulingManager& S,
|
||||
// we choose them so that subsequent choices will be correctly tested
|
||||
// for feasibility, w.r.t. higher priority choices for the same cycle.
|
||||
//
|
||||
while (S.getNumChoices() < S.nslots - startSlot)
|
||||
{
|
||||
while (S.getNumChoices() < S.nslots - startSlot) {
|
||||
const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
|
||||
if (nextNode == NULL)
|
||||
break; // no more instructions for this cycle
|
||||
|
||||
if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0)
|
||||
{
|
||||
if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0) {
|
||||
delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
|
||||
if (delaySlotInfo != NULL)
|
||||
{
|
||||
if (delaySlotInfo != NULL) {
|
||||
if (indexForBreakingNode < S.nslots)
|
||||
// cannot issue a delayed instr in the same cycle as one
|
||||
// that breaks the issue group or as another delayed instr
|
||||
@ -747,9 +737,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
else
|
||||
indexForDelayedInstr = S.getNumChoices();
|
||||
}
|
||||
}
|
||||
else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode()))
|
||||
{
|
||||
} else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode())) {
|
||||
if (indexForBreakingNode < S.nslots)
|
||||
// have a breaking instruction already so throw this one away
|
||||
nextNode = NULL;
|
||||
@ -757,12 +745,10 @@ FindSlotChoices(SchedulingManager& S,
|
||||
indexForBreakingNode = S.getNumChoices();
|
||||
}
|
||||
|
||||
if (nextNode != NULL)
|
||||
{
|
||||
if (nextNode != NULL) {
|
||||
S.addChoice(nextNode);
|
||||
|
||||
if (S.schedInfo.isSingleIssue(nextNode->getOpCode()))
|
||||
{
|
||||
if (S.schedInfo.isSingleIssue(nextNode->getOpCode())) {
|
||||
assert(S.getNumChoices() == 1 &&
|
||||
"Prioritizer returned invalid instr for this cycle!");
|
||||
break;
|
||||
@ -786,8 +772,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
{ // No instructions that break the issue group or that have delay slots.
|
||||
// This is the common case, so handle it separately for efficiency.
|
||||
|
||||
if (S.getNumChoices() == 1)
|
||||
{
|
||||
if (S.getNumChoices() == 1) {
|
||||
MachineOpCode opCode = S.getChoice(0)->getOpCode();
|
||||
unsigned int s;
|
||||
for (s=startSlot; s < S.nslots; s++)
|
||||
@ -795,20 +780,15 @@ FindSlotChoices(SchedulingManager& S,
|
||||
break;
|
||||
assert(s < S.nslots && "No feasible slot for this opCode?");
|
||||
S.addChoiceToSlot(s, S.getChoice(0));
|
||||
}
|
||||
else
|
||||
{
|
||||
for (unsigned i=0; i < S.getNumChoices(); i++)
|
||||
{
|
||||
} else {
|
||||
for (unsigned i=0; i < S.getNumChoices(); i++) {
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
for (unsigned int s=startSlot; s < S.nslots; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
S.addChoiceToSlot(s, S.getChoice(i));
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (indexForDelayedInstr < S.nslots)
|
||||
{
|
||||
} else if (indexForDelayedInstr < S.nslots) {
|
||||
// There is an instruction that needs delay slots.
|
||||
// Try to assign that instruction to a higher slot than any other
|
||||
// instructions in the group, so that its delay slots can go
|
||||
@ -829,23 +809,20 @@ FindSlotChoices(SchedulingManager& S,
|
||||
// Find the last possible slot for the delayed instruction that leaves
|
||||
// at least `d' slots vacant after it (d = #delay slots)
|
||||
for (int s = S.nslots-ndelays-1; s >= (int) startSlot; s--)
|
||||
if (S.schedInfo.instrCanUseSlot(delayOpCode, s))
|
||||
{
|
||||
if (S.schedInfo.instrCanUseSlot(delayOpCode, s)) {
|
||||
delayedNodeSlot = s;
|
||||
break;
|
||||
}
|
||||
|
||||
highestSlotUsed = -1;
|
||||
for (unsigned i=0; i < S.getNumChoices() - 1; i++)
|
||||
{
|
||||
for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
|
||||
// Try to assign every other instruction to a lower numbered
|
||||
// slot than delayedNodeSlot.
|
||||
MachineOpCode opCode =S.getChoice(i)->getOpCode();
|
||||
bool noSlotFound = true;
|
||||
unsigned int s;
|
||||
for (s=startSlot; s < delayedNodeSlot; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
{
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s)) {
|
||||
S.addChoiceToSlot(s, S.getChoice(i));
|
||||
noSlotFound = false;
|
||||
}
|
||||
@ -855,8 +832,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
// the next cycle.
|
||||
if (noSlotFound)
|
||||
for ( ; s < S.nslots; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
{
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s)) {
|
||||
S.addChoiceToSlot(s, S.getChoice(i));
|
||||
break;
|
||||
}
|
||||
@ -874,16 +850,14 @@ FindSlotChoices(SchedulingManager& S,
|
||||
// slots for the node at the same time.
|
||||
cycles_t dcycle = S.getTime();
|
||||
unsigned int dslot = highestSlotUsed + 1;
|
||||
if (dslot == S.nslots)
|
||||
{
|
||||
if (dslot == S.nslots) {
|
||||
dslot = 0;
|
||||
++dcycle;
|
||||
}
|
||||
delaySlotInfo->recordChosenSlot(dcycle, dslot);
|
||||
getDelaySlotInfo = delaySlotInfo;
|
||||
}
|
||||
else
|
||||
{ // There is an instruction that breaks the issue group.
|
||||
} else {
|
||||
// There is an instruction that breaks the issue group.
|
||||
// For such an instruction, assign to the last possible slot in
|
||||
// the current group, and then don't assign any other instructions
|
||||
// to later slots.
|
||||
@ -894,8 +868,7 @@ FindSlotChoices(SchedulingManager& S,
|
||||
|
||||
// Find the last possible slot for this instruction.
|
||||
for (int s = S.nslots-1; s >= (int) startSlot; s--)
|
||||
if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s))
|
||||
{
|
||||
if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s)) {
|
||||
breakingSlot = s;
|
||||
break;
|
||||
}
|
||||
@ -916,10 +889,8 @@ FindSlotChoices(SchedulingManager& S,
|
||||
bool foundLowerSlot = false;
|
||||
nslotsToUse = S.nslots; // May be modified in the loop
|
||||
for (unsigned int s=startSlot; s < nslotsToUse; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
{
|
||||
if (breakingSlot < S.nslots && s < breakingSlot)
|
||||
{
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s)) {
|
||||
if (breakingSlot < S.nslots && s < breakingSlot) {
|
||||
foundLowerSlot = true;
|
||||
nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
|
||||
}
|
||||
@ -934,19 +905,16 @@ FindSlotChoices(SchedulingManager& S,
|
||||
// Assign the breaking instruction (if any) to a single slot
|
||||
// Otherwise, just ignore the instruction. It will simply be
|
||||
// scheduled in a later cycle.
|
||||
if (breakingSlot < S.nslots)
|
||||
{
|
||||
if (breakingSlot < S.nslots) {
|
||||
S.addChoiceToSlot(breakingSlot, breakingNode);
|
||||
nslotsToUse = breakingSlot;
|
||||
}
|
||||
else
|
||||
} else
|
||||
nslotsToUse = S.nslots;
|
||||
|
||||
// For lower priority instructions than the one that breaks the
|
||||
// group, only assign them to slots lower than the breaking slot.
|
||||
// Otherwise, just ignore the instruction.
|
||||
for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++)
|
||||
{
|
||||
for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
|
||||
MachineOpCode opCode = S.getChoice(i)->getOpCode();
|
||||
for (unsigned int s=startSlot; s < nslotsToUse; s++)
|
||||
if (S.schedInfo.instrCanUseSlot(opCode, s))
|
||||
@ -970,8 +938,7 @@ ChooseOneGroup(SchedulingManager& S)
|
||||
// Choose up to `nslots' feasible instructions and their possible slots.
|
||||
unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
|
||||
|
||||
while (numIssued == 0)
|
||||
{
|
||||
while (numIssued == 0) {
|
||||
S.updateTime(S.getTime()+1);
|
||||
numIssued = FindSlotChoices(S, getDelaySlotInfo);
|
||||
}
|
||||
@ -982,14 +949,11 @@ ChooseOneGroup(SchedulingManager& S)
|
||||
numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
|
||||
|
||||
// Print trace of scheduled instructions before newly ready ones
|
||||
if (SchedDebugLevel >= Sched_PrintSchedTrace)
|
||||
{
|
||||
for (cycles_t c = firstCycle; c <= S.getTime(); c++)
|
||||
{
|
||||
if (SchedDebugLevel >= Sched_PrintSchedTrace) {
|
||||
for (cycles_t c = firstCycle; c <= S.getTime(); c++) {
|
||||
std::cerr << " Cycle " << (long)c <<" : Scheduled instructions:\n";
|
||||
const InstrGroup* igroup = S.isched.getIGroup(c);
|
||||
for (unsigned int s=0; s < S.nslots; s++)
|
||||
{
|
||||
for (unsigned int s=0; s < S.nslots; s++) {
|
||||
std::cerr << " ";
|
||||
if ((*igroup)[s] != NULL)
|
||||
std::cerr << * ((*igroup)[s])->getMachineInstr() << "\n";
|
||||
@ -1011,8 +975,7 @@ ForwardListSchedule(SchedulingManager& S)
|
||||
|
||||
S.schedPrio.initialize();
|
||||
|
||||
while ((N = S.schedPrio.getNumReady()) > 0)
|
||||
{
|
||||
while ((N = S.schedPrio.getNumReady()) > 0) {
|
||||
cycles_t nextCycle = S.getTime();
|
||||
|
||||
// Choose one group of instructions for a cycle, plus any delay slot
|
||||
@ -1026,12 +989,10 @@ ForwardListSchedule(SchedulingManager& S)
|
||||
// Notify the priority manager of scheduled instructions and mark
|
||||
// any successors that may now be ready
|
||||
//
|
||||
for (cycles_t c = nextCycle; c <= S.getTime(); c++)
|
||||
{
|
||||
for (cycles_t c = nextCycle; c <= S.getTime(); c++) {
|
||||
const InstrGroup* igroup = S.isched.getIGroup(c);
|
||||
for (unsigned int s=0; s < S.nslots; s++)
|
||||
if ((node = (*igroup)[s]) != NULL)
|
||||
{
|
||||
if ((node = (*igroup)[s]) != NULL) {
|
||||
S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
|
||||
MarkSuccessorsReady(S, node);
|
||||
}
|
||||
@ -1092,8 +1053,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
|
||||
// instruction can be reordered relative to the branch. We simply check
|
||||
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
|
||||
//
|
||||
if (nodeIsPredecessor)
|
||||
{
|
||||
if (nodeIsPredecessor) {
|
||||
bool onlyCDEdgeToBranch = true;
|
||||
for (SchedGraphNode::const_iterator OEI = node->beginOutEdges();
|
||||
OEI != node->endOutEdges(); ++OEI)
|
||||
@ -1120,14 +1080,13 @@ MarkNodeForDelaySlot(SchedulingManager& S,
|
||||
const SchedGraphNode* brNode,
|
||||
bool nodeIsPredecessor)
|
||||
{
|
||||
if (nodeIsPredecessor)
|
||||
{ // If node is in the same basic block (i.e., preceeds brNode),
|
||||
if (nodeIsPredecessor) {
|
||||
// If node is in the same basic block (i.e., preceeds brNode),
|
||||
// remove it and all its incident edges from the graph. Make sure we
|
||||
// add dummy edges for pred/succ nodes that become entry/exit nodes.
|
||||
graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
|
||||
}
|
||||
else
|
||||
{ // If the node was from a target block, add the node to the graph
|
||||
} else {
|
||||
// If the node was from a target block, add the node to the graph
|
||||
// and add a CD edge from brNode to node.
|
||||
assert(0 && "NOT IMPLEMENTED YET");
|
||||
}
|
||||
@ -1173,8 +1132,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
|
||||
// Note that this is the most efficient code when only 1 (or even 2)
|
||||
// values need to be selected.
|
||||
//
|
||||
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
|
||||
{
|
||||
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
|
||||
unsigned lmin =
|
||||
mii.maxLatency(mdelayNodeVec[0]->getOpCode());
|
||||
unsigned minIndex = 0;
|
||||
@ -1202,6 +1160,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
|
||||
//
|
||||
static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
|
||||
SchedGraphNode* node,
|
||||
// FIXME: passing vector BY VALUE!!!
|
||||
std::vector<SchedGraphNode*> sdelayNodeVec,
|
||||
SchedGraph* graph)
|
||||
{
|
||||
@ -1234,8 +1193,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
|
||||
if (mii.isNop(MBB[i]->getOpCode()))
|
||||
if (sdelayNodeVec.size() < ndelays)
|
||||
sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
|
||||
else
|
||||
{
|
||||
else {
|
||||
nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
|
||||
|
||||
//remove the MI from the Machine Code For Instruction
|
||||
@ -1310,8 +1268,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
|
||||
// Compute a vector of the nodes chosen for delay slots and then
|
||||
// mark delay slots to replace NOPs with these useful instructions.
|
||||
//
|
||||
if (brInstr != NULL)
|
||||
{
|
||||
if (brInstr != NULL) {
|
||||
SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
|
||||
FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
|
||||
ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
|
||||
@ -1347,11 +1304,9 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
|
||||
S.scheduleInstr(brNode, nextSlot, nextTime);
|
||||
|
||||
for (unsigned d=0; d < ndelays; d++)
|
||||
{
|
||||
for (unsigned d=0; d < ndelays; d++) {
|
||||
++nextSlot;
|
||||
if (nextSlot == S.nslots)
|
||||
{
|
||||
if (nextSlot == S.nslots) {
|
||||
nextSlot = 0;
|
||||
nextTime++;
|
||||
}
|
||||
@ -1361,8 +1316,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
// We do *not* check for flow dependences but rely on pipeline
|
||||
// interlocks to resolve them. Machines without interlocks
|
||||
// will require this code to be modified.
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++)
|
||||
{
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++) {
|
||||
const SchedGraphNode* dnode = delayNodeVec[i];
|
||||
if ( ! S.isScheduled(dnode)
|
||||
&& S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
|
||||
@ -1388,12 +1342,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
nextSlot = delayedNodeSlotNum;
|
||||
nextTime = delayedNodeCycle;
|
||||
for (unsigned i=0; i < delayNodeVec.size(); i++)
|
||||
if (! S.isScheduled(delayNodeVec[i]))
|
||||
{
|
||||
if (! S.isScheduled(delayNodeVec[i])) {
|
||||
do { // find the next empty slot
|
||||
++nextSlot;
|
||||
if (nextSlot == S.nslots)
|
||||
{
|
||||
if (nextSlot == S.nslots) {
|
||||
nextSlot = 0;
|
||||
nextTime++;
|
||||
}
|
||||
@ -1507,8 +1459,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
|
||||
{
|
||||
SchedGraphSet graphSet(&F, target);
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
|
||||
{
|
||||
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
|
||||
std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
|
||||
graphSet.dump();
|
||||
}
|
||||
@ -1531,8 +1482,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
|
||||
RecordSchedule(MBB, S); // records schedule in BB
|
||||
}
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintMachineCode)
|
||||
{
|
||||
if (SchedDebugLevel >= Sched_PrintMachineCode) {
|
||||
std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
|
||||
MachineFunction::get(&F).dump();
|
||||
}
|
||||
|
@ -257,7 +257,8 @@ SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
|
||||
if (addDummyEdges &&
|
||||
srcNode != getRoot() &&
|
||||
srcNode->beginOutEdges() == srcNode->endOutEdges())
|
||||
{ // srcNode has no more out edges, so add an edge to dummy EXIT node
|
||||
{
|
||||
// srcNode has no more out edges, so add an edge to dummy EXIT node
|
||||
assert(node != getLeaf() && "Adding edge that was just removed?");
|
||||
(void) new SchedGraphEdge(srcNode, getLeaf(),
|
||||
SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
|
||||
@ -490,9 +491,8 @@ SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
|
||||
if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
|
||||
break;
|
||||
assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
|
||||
}
|
||||
else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
|
||||
{ // Add incoming/outgoing edges from/to preceding/later calls
|
||||
} else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
|
||||
// Add incoming/outgoing edges from/to preceding/later calls
|
||||
SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
|
||||
int j=0;
|
||||
for ( ; j <= lastCallNodeIdx; j++)
|
||||
@ -522,26 +522,22 @@ SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
|
||||
RefVec& regRefVec = (*I).second;
|
||||
|
||||
// regRefVec is ordered by control flow order in the basic block
|
||||
for (unsigned i=0; i < regRefVec.size(); ++i)
|
||||
{
|
||||
for (unsigned i=0; i < regRefVec.size(); ++i) {
|
||||
SchedGraphNode* node = regRefVec[i].first;
|
||||
unsigned int opNum = regRefVec[i].second;
|
||||
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
|
||||
bool isDefAndUse =
|
||||
node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
|
||||
|
||||
for (unsigned p=0; p < i; ++p)
|
||||
{
|
||||
for (unsigned p=0; p < i; ++p) {
|
||||
SchedGraphNode* prevNode = regRefVec[p].first;
|
||||
if (prevNode != node)
|
||||
{
|
||||
if (prevNode != node) {
|
||||
unsigned int prevOpNum = regRefVec[p].second;
|
||||
bool prevIsDef =
|
||||
prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
|
||||
bool prevIsDefAndUse =
|
||||
prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
|
||||
if (isDef)
|
||||
{
|
||||
if (isDef) {
|
||||
if (prevIsDef)
|
||||
new SchedGraphEdge(prevNode, node, regNum,
|
||||
SchedGraphEdge::OutputDep);
|
||||
@ -582,17 +578,16 @@ SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
|
||||
if ((*I).first == refNode)
|
||||
continue; // Dont add any self-loops
|
||||
|
||||
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
|
||||
{ // (*).first is before refNode
|
||||
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
|
||||
// (*).first is before refNode
|
||||
if (refNodeIsDef)
|
||||
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
||||
SchedGraphEdge::OutputDep);
|
||||
if (refNodeIsUse)
|
||||
(void) new SchedGraphEdge((*I).first, refNode, defValue,
|
||||
SchedGraphEdge::TrueDep);
|
||||
}
|
||||
else
|
||||
{ // (*).first is after refNode
|
||||
} else {
|
||||
// (*).first is after refNode
|
||||
if (refNodeIsDef)
|
||||
(void) new SchedGraphEdge(refNode, (*I).first, defValue,
|
||||
SchedGraphEdge::OutputDep);
|
||||
@ -692,8 +687,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
||||
{
|
||||
int regNum = mop.getMachineRegNum();
|
||||
if (regNum != target.getRegInfo().getZeroRegNum())
|
||||
regToRefVecMap[mop.getMachineRegNum()].push_back(
|
||||
std::make_pair(node, i));
|
||||
regToRefVecMap[mop.getMachineRegNum()]
|
||||
.push_back(std::make_pair(node, i));
|
||||
continue; // nothing more to do
|
||||
}
|
||||
|
||||
@ -903,8 +898,7 @@ std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
|
||||
|
||||
if (node.getMachineInstr() == NULL)
|
||||
os << "(Dummy node)\n";
|
||||
else
|
||||
{
|
||||
else {
|
||||
os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
|
||||
os << node.inEdges.size() << " Incoming Edges:\n";
|
||||
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
|
||||
|
Loading…
Reference in New Issue
Block a user