diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index bf8499353fb..3f7f9f73327 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1183,7 +1183,10 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
         RC = X86::FR64RegisterClass;
       else {
         assert(MVT::isVector(RegVT));
-        RC = X86::VR128RegisterClass;
+        if (MVT::getSizeInBits(RegVT) == 64)
+          RC = X86::VR64RegisterClass;
+        else
+          RC = X86::VR128RegisterClass;
       }
 
       unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);