mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-24 06:25:18 +00:00
remove 300 lines of code that is now dead in the MSP430 backend
now that isel handles chains more aggressively. This also allows us to make isLegalToFold non-virtual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97597 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -97,7 +97,7 @@ public:
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root.
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/// U can be folded during instruction selection that starts at Root.
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virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
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bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
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bool IgnoreChains = false) const;
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bool IgnoreChains = false) const;
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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@@ -30,13 +30,8 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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using namespace llvm;
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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namespace {
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namespace {
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struct MSP430ISelAddressMode {
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struct MSP430ISelAddressMode {
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enum {
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enum {
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@@ -114,9 +109,6 @@ namespace {
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Lowering(*TM.getTargetLowering()),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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Subtarget(*TM.getSubtargetImpl()) { }
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virtual void PreprocessISelDAG();
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virtual void PostprocessISelDAG();
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virtual const char *getPassName() const {
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virtual const char *getPassName() const {
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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}
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}
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@@ -125,10 +117,6 @@ namespace {
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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#if 0
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bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
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#endif
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virtual bool
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virtual bool
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps);
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std::vector<SDValue> &OutOps);
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@@ -137,8 +125,6 @@ namespace {
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#include "MSP430GenDAGISel.inc"
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#include "MSP430GenDAGISel.inc"
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private:
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private:
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DenseMap<SDNode*, SDNode*> RMWStores;
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void PreprocessForRMW();
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SDNode *Select(SDNode *N);
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SDNode *Select(SDNode *N);
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SDNode *SelectIndexedLoad(SDNode *Op);
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SDNode *SelectIndexedLoad(SDNode *Op);
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SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
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SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
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@@ -206,10 +192,7 @@ bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM)
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}
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}
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bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
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bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
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DEBUG({
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DEBUG(errs() << "MatchAddress: "; AM.dump());
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errs() << "MatchAddress: ";
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AM.dump();
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});
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switch (N.getOpcode()) {
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switch (N.getOpcode()) {
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default: break;
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default: break;
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@@ -325,273 +308,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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return false;
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return false;
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}
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}
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#if 0
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bool MSP430DAGToDAGISel::IsLegalToFold(SDValue N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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/// RMW preprocessing creates the following code:
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/// [Load1]
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/// ^ ^
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/// / |
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/// / |
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/// [Load2] |
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/// ^ ^ |
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/// | | |
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/// | \-|
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// The path Store => Load2 => Load1 is via chain. Note that in general it is
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/// not allowed to fold Load1 into Op (and Store) since it will creates a
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/// cycle. However, this is perfectly legal for the loads moved below the
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/// TokenFactor by PreprocessForRMW. Query the map Store => Load1 (created
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/// during preprocessing) to determine whether it's legal to introduce such
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/// "cycle" for a moment.
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DenseMap<SDNode*, SDNode*>::const_iterator I = RMWStores.find(Root);
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if (I != RMWStores.end() && I->second == N.getNode())
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return true;
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// Proceed to 'generic' cycle finder code
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return SelectionDAGISel::IsLegalToFold(N, U, Root);
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}
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#endif
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
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if (Load.getNode() == TF.getOperand(i).getNode())
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(TF.getOperand(i));
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SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
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Load.getOperand(1),
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Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// MoveBelowTokenFactor2 - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result. This a version which sinks two loads below token factor.
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/// Look into PreprocessForRMW comments for explanation of transform.
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static void MoveBelowTokenFactor2(SelectionDAG *CurDAG,
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SDValue Load1, SDValue Load2,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) {
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SDNode* N = TF.getOperand(i).getNode();
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if (Load2.getNode() == N)
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Ops.push_back(Load2.getOperand(0));
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else if (Load1.getNode() != N)
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Ops.push_back(TF.getOperand(i));
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}
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SDValue NewTF = SDValue(CurDAG->MorphNodeTo(TF.getNode(),
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TF.getOpcode(),
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TF.getNode()->getVTList(),
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&Ops[0], Ops.size()), TF.getResNo());
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SDValue NewLoad2 = CurDAG->UpdateNodeOperands(Load2, NewTF,
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Load2.getOperand(1),
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Load2.getOperand(2));
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SDValue NewLoad1 = CurDAG->UpdateNodeOperands(Load1, NewLoad2.getValue(1),
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Load1.getOperand(1),
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Load1.getOperand(2));
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CurDAG->UpdateNodeOperands(Store,
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NewLoad1.getValue(1),
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Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isAllowedToSink - return true if N a load which can be moved below token
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/// factor. Basically, the load should be non-volatile and has single use.
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static bool isLoadAllowedToSink(SDValue N, SDValue Chain) {
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if (N.getOpcode() == ISD::BIT_CONVERT)
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N = N.getOperand(0);
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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return (N.hasOneUse() &&
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LD->hasNUsesOfValue(1, 1) &&
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LD->isOperandOf(Chain.getNode()));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
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/// The chain produced by the load must only be used by the store's chain
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/// operand, otherwise this may produce a cycle in the DAG.
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static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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SDValue &Load) {
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if (isLoadAllowedToSink(N, Chain) &&
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N.getOperand(1) == Address) {
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Load = N;
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return true;
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}
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return false;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// This is only run if not in -O0 mode.
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/// This allows the instruction selector to pick more read-modify-write
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/// instructions. This is a common case:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \-
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/// / |
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/// [TokenFactor] [Op]
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/// ^ ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// The fact the store's chain operand != load's chain will prevent the
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/// (store (op (load))) instruction from being selected. We can transform it to:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [TokenFactor]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// | \-
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// We also recognize the case where second operand of Op is load as well and
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/// move it below token factor as well creating DAG as follows:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [TokenFactor]
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/// ^
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/// |
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/// [Load1]
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/// ^ ^
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/// / |
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/// / |
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/// [Load2] |
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/// ^ ^ |
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/// | | |
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/// | \-|
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// This allows selection of mem-mem instructions. Yay!
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void MSP430DAGToDAGISel::PreprocessForRMW() {
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return;
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E; ++I) {
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if (!ISD::isNON_TRUNCStore(I))
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continue;
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SDValue Chain = I->getOperand(0);
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if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
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continue;
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SDValue N1 = I->getOperand(1);
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SDValue N2 = I->getOperand(2);
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if ((N1.getValueType().isFloatingPoint() &&
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!N1.getValueType().isVector()) ||
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!N1.hasOneUse())
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continue;
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unsigned RModW = 0;
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SDValue Load1, Load2;
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unsigned Opcode = N1.getNode()->getOpcode();
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switch (Opcode) {
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case ISD::ADD:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (isRMWLoad(N10, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N11, Chain)) {
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Load2 = N11;
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RModW = 2;
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} else
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RModW = 1;
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} else if (isRMWLoad(N11, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N10, Chain)) {
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Load2 = N10;
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RModW = 2;
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} else
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RModW = 1;
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}
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break;
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}
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case ISD::SUB:
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case ISD::SUBC:
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case ISD::SUBE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (isRMWLoad(N10, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N11, Chain)) {
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Load2 = N11;
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RModW = 2;
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} else
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RModW = 1;
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}
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break;
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}
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}
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NumLoadMoved += RModW;
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if (RModW == 1)
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MoveBelowTokenFactor(CurDAG, Load1, SDValue(I, 0), Chain);
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else if (RModW == 2) {
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MoveBelowTokenFactor2(CurDAG, Load1, Load2, SDValue(I, 0), Chain);
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SDNode* Store = I;
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RMWStores[Store] = Load2.getNode();
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}
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}
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}
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static bool isValidIndexedLoad(const LoadSDNode *LD) {
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static bool isValidIndexedLoad(const LoadSDNode *LD) {
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
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if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
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@@ -674,14 +390,6 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
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}
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}
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void MSP430DAGToDAGISel::PreprocessISelDAG() {
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PreprocessForRMW();
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}
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void MSP430DAGToDAGISel::PostprocessISelDAG() {
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RMWStores.clear();
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}
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SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
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SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
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DebugLoc dl = Node->getDebugLoc();
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DebugLoc dl = Node->getDebugLoc();
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Reference in New Issue
Block a user