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ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.

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LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2013-09-27 10:30:18 +00:00
parent ba616ef023
commit 6b968eccd7
2 changed files with 20 additions and 0 deletions
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11
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5355,6 +5355,17 @@ validateInstruction(MCInst &Inst,
"destination operands must be sequential");
return false;
}
case ARM::t2LDRDi8:
case ARM::t2LDRD_PRE:
case ARM::t2LDRD_POST: {
// Rt2 must different from Rt.
unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
if (Rt2 == Rt)
return Error(Operands[3]->getStartLoc(),
"destination operands can't be identical");
return false;
}
case ARM::STRD: {
// Rt2 must be Rt + 1.
unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());

9
test/MC/ARM/thumb2-ldrd.s Normal file
View File

@ -0,0 +1,9 @@
// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \
// RUN: < %s >/dev/null 2> %t
// RUN: grep "error: destination operands can't be identical" %t | count 4
// rdar://14479780
ldrd r0, r0, [pc, #0]
ldrd r0, r0, [r1, #4]
ldrd r0, r0, [r1], #4
ldrd r0, r0, [r1, #4]!