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For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -184,7 +184,7 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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int64_t Remainder = FrameSize - Base;
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int64_t Remainder = FrameSize - Base;
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
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if (isInt<16>(-Remainder))
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if (isInt<16>(-Remainder))
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BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(-Remainder);
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BuildAddiuSpImm(MBB, I, DL, -Remainder);
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else
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else
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adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
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adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
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}
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}
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@ -225,7 +225,7 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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// returns largest possible n bit unsigned integer
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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int64_t Remainder = FrameSize - Base;
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if (isInt<16>(Remainder))
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if (isInt<16>(Remainder))
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BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Remainder);
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BuildAddiuSpImm(MBB, I, DL, Remainder);
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else
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else
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adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
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adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
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BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
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BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
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@ -299,7 +299,7 @@ void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock::iterator I) const {
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
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if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
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BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Amount);
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BuildAddiuSpImm(MBB, I, DL, Amount);
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else
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else
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adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
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adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
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}
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}
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@ -400,6 +400,15 @@ void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
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}
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}
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void Mips16InstrInfo::BuildAddiuSpImm(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL, int64_t Imm) const {
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if (validSpImm8(Imm))
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BuildMI(MBB, II, DL, get(Mips::AddiuSpImm16)).addImm(Imm);
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else
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BuildMI(MBB, II, DL, get(Mips::AddiuSpImmX16)).addImm(Imm);
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}
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const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
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const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
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return new Mips16InstrInfo(TM);
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return new Mips16InstrInfo(TM);
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}
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}
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@ -86,6 +86,18 @@ public:
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MachineBasicBlock::iterator II, DebugLoc DL,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const;
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unsigned &NewImm) const;
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static bool validSpImm8(int offset) {
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return ((offset & 7) == 0) && isInt<11>(offset);
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}
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//
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// build the proper one based on the Imm field
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//
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void BuildAddiuSpImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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int64_t Imm) const;
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private:
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private:
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virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
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virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
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@ -31,6 +31,21 @@ def mem16_ea : Operand<i32> {
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let EncoderMethod = "getMemEncoding";
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let EncoderMethod = "getMemEncoding";
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}
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}
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//
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//
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// I8 instruction format
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//
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class FI816_ins_base<bits<3> _func, string asmstr,
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string asmstr2, InstrItinClass itin>:
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FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
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[], itin>;
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class FI816_SP_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
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//
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//
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// RI instruction format
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// RI instruction format
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//
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//
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@ -451,6 +466,13 @@ def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
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// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
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// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
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// To add a constant to the stack pointer.
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// To add a constant to the stack pointer.
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//
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//
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def AddiuSpImm16
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: FI816_SP_ins<0b011, "addiu", IIAlu> {
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let Defs = [SP];
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let Uses = [SP];
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let AddedComplexity = 5;
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}
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def AddiuSpImmX16
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def AddiuSpImmX16
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: FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
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: FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
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let Defs = [SP];
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let Defs = [SP];
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31
test/CodeGen/Mips/align16.ll
Normal file
31
test/CodeGen/Mips/align16.ll
Normal file
@ -0,0 +1,31 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16
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@i = global i32 25, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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define void @p(i32* %i) nounwind {
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entry:
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ret void
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}
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define void @foo() nounwind {
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entry:
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%y = alloca [512 x i32], align 4
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%x = alloca i32, align 8
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%zz = alloca i32, align 4
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%z = alloca i32, align 4
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%0 = load i32* @i, align 4
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%arrayidx = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
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store i32 %0, i32* %arrayidx, align 4
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%1 = load i32* @i, align 4
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store i32 %1, i32* %x, align 8
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call void @p(i32* %x)
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%arrayidx1 = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10
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call void @p(i32* %arrayidx1)
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ret void
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}
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; 16: save $ra, $s0, $s1, 2040
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; 16: addiu $sp, -48 # 16 bit inst
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; 16: addiu $sp, 48 # 16 bit inst
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; 16: restore $ra, $s0, $s1, 2040
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