From 6baf46dbeab86dd7a35a9737bbdc5c67bee0bf69 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 16 Dec 2010 00:50:33 +0000 Subject: [PATCH] Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for it. I.e., it was always an immediate value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmBackend.cpp | 4 ---- lib/Target/ARM/ARMFixupKinds.h | 3 --- lib/Target/ARM/ARMMCCodeEmitter.cpp | 12 +----------- 3 files changed, 1 insertion(+), 18 deletions(-) diff --git a/lib/Target/ARM/ARMAsmBackend.cpp b/lib/Target/ARM/ARMAsmBackend.cpp index 67f2c710571..e4acd667307 100644 --- a/lib/Target/ARM/ARMAsmBackend.cpp +++ b/lib/Target/ARM/ARMAsmBackend.cpp @@ -237,9 +237,6 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // 'off by 4' is implicitly handled by the half-word ordering of the // Thumb encoding, so we only need to adjust by 2 here. return ((Value - 2) >> 2) & 0xff; - case ARM::fixup_arm_thumb_ldst: - // Offset by 4. - return ((Value - 4) & 0x1f) << 6; case ARM::fixup_arm_thumb_cb: { // Offset by 4 and don't encode the lower bit, which is always 0. uint32_t Binary = (Value - 4) >> 1; @@ -368,7 +365,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case ARM::fixup_arm_thumb_br: case ARM::fixup_arm_thumb_cb: - case ARM::fixup_arm_thumb_ldst: return 2; case ARM::fixup_arm_ldst_pcrel_12: diff --git a/lib/Target/ARM/ARMFixupKinds.h b/lib/Target/ARM/ARMFixupKinds.h index f1683732b28..3e0bd0e7b7a 100644 --- a/lib/Target/ARM/ARMFixupKinds.h +++ b/lib/Target/ARM/ARMFixupKinds.h @@ -65,9 +65,6 @@ enum Fixups { // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs. fixup_arm_thumb_cp, - // fixup_arm_thumb_ldst - Fixup for Thumb load/store instrs. - fixup_arm_thumb_ldst, - // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions. fixup_arm_thumb_bcc, diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 8a779cebb95..2f210c3ad2d 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -68,7 +68,6 @@ public: { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_arm_thumb_ldst", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_movt_hi16", 0, 16, 0 }, { "fixup_arm_movw_lo16", 0, 16, 0 }, @@ -824,16 +823,7 @@ getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); unsigned Rn = getARMRegisterNumbering(MO.getReg()); - unsigned Imm5 = 0; - - if (MO1.isExpr()) { - const MCExpr *Expr = MO.getExpr(); - MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst); - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); - } else { - Imm5 = MO1.getImm(); - } - + unsigned Imm5 = Imm5 = MO1.getImm(); return ((Imm5 & 0x1f) << 3) | Rn; }