From 6bd6ede7d758a815cc640839658fda50922e5eea Mon Sep 17 00:00:00 2001 From: Gabor Greif Date: Mon, 12 Oct 2009 16:27:44 +0000 Subject: [PATCH] more typewriter face git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83852 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/ReleaseNotes-2.6.html | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/docs/ReleaseNotes-2.6.html b/docs/ReleaseNotes-2.6.html index 5aa8d010f7e..60c0c4019a0 100644 --- a/docs/ReleaseNotes-2.6.html +++ b/docs/ReleaseNotes-2.6.html @@ -637,7 +637,8 @@ it run faster:

commutable operations, various spiller peephole optimizations, and can now coalesce cross-register-class copies.
  • Tblgen now supports multiclass inheritance and a number of new string and - list operations like !(subst), !(foreach), !car, !cdr, !null, !if, !cast. + list operations like !(subst), !(foreach), !car, + !cdr, !null, !if, !cast. These make the .td files more expressive and allow more aggressive factoring of duplication across instruction patterns.
  • Target-specific intrinsics can now be added without having to hack VMCore to @@ -656,12 +657,13 @@ it run faster:

    from the compiler. It works well for many simple C testcases, but doesn't support exception handling, debug info, inline assembly, etc.
  • Targets can now specify register allocation hints through - MachineRegisterInfo::setRegAllocationHint. A regalloc hint consists of hint - type and physical register number. A hint type of zero specifies a register - allocation preference. Other hint type values are target specific which are - resolved by TargetRegisterInfo::ResolveRegAllocHint. An example is the ARM - target which uses register hints to request that the register allocator - provide an even / odd register pair to two virtual registers.
    • + MachineRegisterInfo::setRegAllocationHint. A regalloc hint consists + of hint type and physical register number. A hint type of zero specifies a + register allocation preference. Other hint type values are target specific + which are resolved by TargetRegisterInfo::ResolveRegAllocHint. An + example is the ARM target which uses register hints to request that the + register allocator provide an even / odd register pair to two virtual + registers. @@ -804,12 +806,13 @@ branched.

    make operations on character ranges and string concatenation to be more efficient. StringRef is just a const char* with a length, Twine is a light-weight rope. -
  • LLVM has new WeakVH, AssertingVH and CallbackVH classes, which make it - easier to write LLVM IR transformations. WeakVH is automatically drops to - null when the referenced Value is deleted, and is updated across a - replaceAllUsesWith operation. AssertingVH aborts the program if the - referenced value is destroyed while it is being referenced. CallbackVH is - a customizable class for handling value references. See LLVM has new WeakVH, AssertingVH and CallbackVH + classes, which make it easier to write LLVM IR transformations. WeakVH + is automatically drops to null when the referenced Value is deleted, + and is updated across a replaceAllUsesWith operation. + AssertingVH aborts the program if the + referenced value is destroyed while it is being referenced. CallbackVH + is a customizable class for handling value references. See ValueHandle.h for more information.
  • The new 'Triple @@ -823,9 +826,9 @@ branched.

    and     reader/writer locks.
  • LLVM has new - SourceMgr and SMLoc classes which implement caret diagnostics and basic - include stack processing for simple parsers. It is used by tablegen, - llvm-mc, the .ll parser and FileCheck.
    • + SourceMgr and SMLoc classes which implement caret + diagnostics and basic include stack processing for simple parsers. It is + used by tablegen, llvm-mc, the .ll parser and FileCheck. @@ -859,7 +862,7 @@ CPU2000).