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ARM: Use non-VFP softcalls on embedded Darwinish targets

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The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1
code to make use of VFP instructions by switching back to ARM mode, they make
no sense for M-class processors which don't even have an ARM mode.

Given that justification, in practice this is a platform ABI decision so the
actual check is based on that rather than CPU features.

rdar://problem/15302004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-10-24 10:37:09 +00:00
parent 3985f6a98d
commit 6c0138e5fc
2 changed files with 23 additions and 1 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -175,7 +175,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
if (Subtarget->isTargetDarwin()) {
if (Subtarget->isTargetIOS()) {
// Uses VFP for Thumb libfuncs if available.
if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
// Single-precision floating-point arithmetic.

22
test/CodeGen/ARM/darwin-eabi.ll Normal file
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@ -0,0 +1,22 @@
; RUN: llc -mtriple=thumbv7m-apple-darwin-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
; RUN: llc -mtriple=thumbv7em-apple-darwin-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
define float @float_op(float %lhs, float %rhs) {
%sum = fadd float %lhs, %rhs
ret float %sum
; CHECK-M3-LABEL: float_op:
; CHECK-M3: blx ___addsf3
; CHECK-M4-LABEL: float_op:
; CHECK-M4: vadd.f32
}
define double @double_op(double %lhs, double %rhs) {
%sum = fadd double %lhs, %rhs
ret double %sum
; CHECK-M3-LABEL: double_op:
; CHECK-M3: blx ___adddf3
; CHECK-M4-LABEL: double_op:
; CHECK-M4: blx ___adddf3
}