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https://github.com/c64scene-ar/llvm-6502.git
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Fix a bug emitting branches that broke a lot of programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19452 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -362,7 +362,7 @@ namespace {
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}
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void EmitCMP(SDOperand LHS, SDOperand RHS);
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bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond);
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bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain, SDOperand Cond);
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void EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
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unsigned RTrue, unsigned RFalse, unsigned RDest);
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unsigned SelectExpr(SDOperand N);
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@ -559,7 +559,8 @@ static void EmitSetCC(MachineBasicBlock *BB, unsigned DestReg,
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/// the Dest block if the Cond condition is true. If we cannot fold this
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/// condition into the branch, return true.
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///
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bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond) {
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bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain,
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SDOperand Cond) {
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// FIXME: Evaluate whether it would be good to emit code like (X < Y) | (A >
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// B) using two conditional branches instead of one condbr, two setcc's, and
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// an or.
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@ -568,6 +569,7 @@ bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond) {
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// And and or set the flags for us, so there is no need to emit a TST of the
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// result. It is only safe to do this if there is only a single use of the
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// AND/OR though, otherwise we don't know it will be emitted here.
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Select(Chain);
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SelectExpr(Cond);
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BuildMI(BB, X86::JNE, 1).addMBB(Dest);
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return false;
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@ -577,7 +579,14 @@ bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond) {
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if (Cond.getOpcode() == ISD::XOR)
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if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(Cond.Val->getOperand(1)))
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if (NC->isAllOnesValue()) {
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unsigned CondR = SelectExpr(Cond.Val->getOperand(0));
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unsigned CondR;
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if (getRegPressure(Chain) > getRegPressure(Cond)) {
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Select(Chain);
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CondR = SelectExpr(Cond.Val->getOperand(0));
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} else {
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CondR = SelectExpr(Cond.Val->getOperand(0));
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Select(Chain);
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}
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BuildMI(BB, X86::TEST8rr, 2).addReg(CondR).addReg(CondR);
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BuildMI(BB, X86::JE, 1).addMBB(Dest);
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return false;
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@ -604,6 +613,7 @@ bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond) {
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case ISD::SETULE: Opc = X86::JBE; break;
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case ISD::SETUGE: Opc = X86::JAE; break;
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}
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Select(Chain);
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EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1));
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BuildMI(BB, Opc, 1).addMBB(Dest);
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return false;
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@ -660,6 +670,7 @@ bool ISel::EmitBranchCC(MachineBasicBlock *Dest, SDOperand Cond) {
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return true; // FIXME: Emit more efficient code for this branch.
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}
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Select(Chain);
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EmitCMP(SetCC->getOperand(0), SetCC->getOperand(1));
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BuildMI(BB, Opc, 1).addMBB(Dest);
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if (Opc2)
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@ -1906,21 +1917,20 @@ void ISel::Select(SDOperand N) {
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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bool ChainFirst =
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getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1));
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if (ChainFirst) Select(N.getOperand(0));
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// Try to fold a setcc into the branch. If this fails, emit a test/jne
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// pair.
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if (EmitBranchCC(Dest, N.getOperand(1))) {
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Tmp1 = SelectExpr(N.getOperand(1));
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if (EmitBranchCC(Dest, N.getOperand(0), N.getOperand(1))) {
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if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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} else {
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Tmp1 = SelectExpr(N.getOperand(1));
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Select(N.getOperand(0));
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}
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BuildMI(BB, X86::TEST8rr, 2).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, X86::JNE, 1).addMBB(Dest);
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}
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if (!ChainFirst) Select(N.getOperand(0));
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return;
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}
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case ISD::LOAD:
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